IDT54FCT244APY 查看數據表（PDF） - Integrated Device Technology
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IDT54FCT244APY Datasheet PDF : 6 Pages
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IDT54/74FCT3244/A
3.3V CMOS OCTAL BUFFER/LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
6V
V CC
Open
V IN
Pulse
Generator
V OUT
D.U.T.
GND
500Ω
50pF
500Ω
RT
CL
2779 drw 03
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
Switch
6V
GND
Open
DEFINITIONS:
2779 lnk 08
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
DATA
INPUT
tSU
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
tSU
ETC.
tH
tREM
tH
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
2779 drw 04
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
1.5V
tW
1.5V
2779 drw 05
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
SAME PHASE
INPUT TRANSITION
tPLH
tPHL
3V
1.5V
0V
VOH
CONTROL
INPUT
tPZL
3V
1.5V
0V
tPLZ
OUTPUT
1.5V
OUTPUT
3V
3V
tPLH
tPHL
VOL
NORMALLY SWITCH
LOW
6V
1.5V
0.3V VOL
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
2779 drw 06
OUTPUT
NORMALLY
HIGH
tPZH
SWITCH
GND
tPHZ
1.5V
0V
0.3V VOH
0V
NOTES:
2779 drw 07
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
3. If VCC is below 3V, input voltage swings should be adjusted not to exceed
VCC.
8.11
5
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