IDT7005S17F 查看數據表（PDF） - Integrated Device Technology

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IDT7005S17F

HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT7005S/L

HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE (5)

Symbol

Parameter

IDT7005X15

Com'l. Only

Min. Max.

IDT7005X17

Com'l. Only

Min. Max.

IDT7005X20

Min. Max.

IDT7005X25

Min. Max. Unit

WRITE CYCLE

tWC

Write Cycle Time

tEW

Chip Enable to End-of-Write(3)

15 —

12 —

17

—

20

—

25

— ns

12

—

15

—

20

— ns

tAW

Address Valid to End-of-Write

tAS

Address Set-up Time(3)

12 —

0—

12

—

15

—

20

— ns

0

—

0

—

0

— ns

tWP

Write Pulse Width

12 —

12

—

15

—

20

— ns

tWR

Write Recovery Time

0—

0

—

0

—

0

— ns

tDW

tHZ

tDH

tWZ

tOW

tSWRD

tSPS

Data Valid to End-of-Write

Output High-Z Time(1, 2)

Data Hold Time(4)

Write Enable to Output in High-Z(1, 2)

Output Active from End-of-Write(1, 2, 4)

SEM Flag Write to Read Time

SEM Flag Contention Window

10 —

— 10

0—

— 10

0—

5—

5—

10

—

15

—

15

— ns

—

10

—

12

—

15 ns

0

—

0

—

0

— ns

—

10

—

12

—

15 ns

0

—

0

—

0

— ns

5

—

5

—

5

— ns

5

—

5

—

5

— ns

Symbol

Parameter

IDT7005X35 IDT7005X55

Min. Max. Min. Max.

IDT7005X70

Mil. Only

Min. Max. Unit

WRITE CYCLE

tWC

Write Cycle Time

tEW

Chip Enable to End-of-Write(3)

35

—

55

—

70

— ns

30

—

45

—

50

— ns

tAW

Address Valid to End-of-Write

tAS

Address Set-up Time(3)

30

—

45

—

50

— ns

0

—

0

—

0

— ns

tWP

Write Pulse Width

25

—

40

—

50

— ns

tWR

Write Recovery Time

0

—

0

—

0

— ns

tDW

tHZ

tDH

tWZ

tOW

tSWRD

tSPS

Data Valid to End-of-Write

Output High-Z Time(1, 2)

Data Hold Time(4)

Write Enable to Output in High-Z(1, 2)

Output Active from End-of-Write(1, 2, 4)

SEM Flag Write to Read Time

SEM Flag Contention Window

15

—

30

—

40

— ns

—

15

—

25

—

30 ns

0

—

0

—

0

— ns

—

15

—

25

—

30 ns

0

—

0

—

0

— ns

5

—

5

—

5

— ns

5

—

5

—

5

— ns

NOTES:

2738 tbl 14

1. Transition is measured ±500mV from Low or High-impedance voltage with the Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization but is not production tested.

3. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.

4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary

over voltage and temperature, the actual tDH will always be smaller than the actual tOW.

5. "X" in part numbers indicates power rating (S or L).

6.06

9

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