IDT7006S17J 查看數據表（PDF） - Integrated Device Technology

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IDT7006S17J

HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT7006S/L

HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM

WAVEFORM OF READ CYCLES(5)

ADDRESS

CE

OE

tAA (4)

tACE (4)

tAOE (4)

R/W

DATAOUT

tLZ (1)

BUSYOUT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

tRC

tBDD (3, 4)

VALID DATA (4)

tOH

tHZ (2)

2739 drw 07

NOTES:

1. Timing depends on which signal is asserted last, OE or CE.

2. Timing depends on which signal is de-asserted first, CE or OE.

3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations

BUSY has no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.

5. SEM = VIH.

TIMING OF POWER-UP POWER-DOWN

CE

tPU

ICC

50%

ISB

tPD

50%

2739 drw 08

6.07

8

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