IDT7024S17GG(2018) 查看數據表（PDF） - Integrated Device Technology

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IDT7024S17GG
(Rev.:2018)

HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM

Waveform of Read Cycles(5)

tRC

ADDR

CE

tAA (4)

tACE (4)

tAOE (4)

OE

UB, LB

tABE (4)

Military, Industrial and Commercial Temperature Ranges

R/W

DATAOUT

tLZ (1)

tOH

VALID DATA(4)

tHZ (2)

BUSYOUT

tBDD (3,4)

2740 drw 07

NOTES:

1. Timing depends on which signal is asserted last, CE, OE, LB, or UB.

2. Timing depends on which signal is de-asserted first, CE, OE, LB, or UB.

3. tBDD delay is required only in cases where opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has

no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last tABE, tAOE, tACE, tAA or tBDD.

5. SEM = VIH.

Timing of Power-Up Power-Down

CE

tPU

ICC

ISB

tPD

,

2740 drw 08

6.942

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