IDT71V3557SA75PF 查看數據表（PDF） - Integrated Device Technology

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IDT71V3557SA75PF

128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs

Integrated Device Technology 

IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Linear Burst Sequence Table (LBO=VSS)

Sequence 1

Sequence 2

Sequence 3

Sequence 4

A1

A0

A1

A0

A1

A0

A1

A0

First Address

0

0

0

1

1

0

1

1

Second Address

0

1

1

0

1

1

0

0

Third Address

1

0

1

1

0

0

0

1

Fourth Address(1)

1

1

0

0

0

1

1

0

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.

5282 tbl 11

Functional Timing Diagram (1)

CYCLE

n+29

n+30

n+31

CLOCK

(2)

ADDRESS

(A0 - A16)

A29

A30

A31

CONTROL(2)

(R/W, ADV/LD, BWx) C29

C30

C31

n+32

A32

C32

n+33

A33

C33

n+34

A34

C34

n+35

A35

C35

n+36

A36

C36

n+37

A37

C37

(2)

DATA

I/O [0:31], I/O P[1:4]

D/Q28

D/Q29

D/Q30

D/Q31

D/Q32

D/Q33

D/Q34

D/Q35

, D/Q36

5282 drw 03

NOTES:

1. This assumes CEN, CE1, CE2 and CE2 are all true.

2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data

delay from the rising edge of clock.

6.1402

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