IDT71V3557SA75PF 查看數據表（PDF） - Integrated Device Technology

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IDT71V3557SA75PF

128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs

Integrated Device Technology 

IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Functional Block Diagram — 256K x 18

LBO

Address A [0:17]

CE1, CE2 CE2

R/W

CEN

ADV/LD

BWx

DQ

DQ

256K x 18 BIT

MEMORY ARRAY

Address

Control

DI DO

DQ

Clk

Control Logic

Clock

OE

TMS

TDI

TCK

TRST

(optional)

JTAG

(SA Version)

TDO

Recommended DC Operating

Conditions

Symbol

Parameter

Min. Typ. Max. Unit

VDD Core Supply Voltage

3.135 3.3 3.465

V

VDDQ I/O Supply Voltage

3.135 3.3 3.465

V

VSS Ground

00

0

V

VIH Input High Voltage - Inputs 2.0 ____ VDD + 0.3 V

VIH Input High Voltage - I/O

2.0 ____ VDDQ + 0.3(2) V

VIL Input Low Voltage

-0.3(1) ____

0.8

V

NOTES:

5282 tbl 04

1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.

2. VIH (max.) = +6.0V for pulse width less than tCYC/2, once per cycle.

6.442

Mux

Sel

Gate

,

Data I/O [0:15], I/O P[1:2]

5282 drw 01a

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