IDT7201LA40L(1997) 查看數據表（PDF） - Integrated Device Technology

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IDT7201LA40L
(Rev.:1997)

CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9, 1,024 x 9

Integrated Device Technology 

IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO

256 x 9, 512 x 9 and 1,024 x 9

MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES

pointer and read pointer is less than or equal to one half of the

total memory of the device. The Half-Full Flag (HF) is then

reset by using rising edge of the read operation.

In the Depth Expansion Mode, Expansion In (XI) is con-

nected to Expansion Out (XO) of the previous device. This

output acts as a signal to the next device in the Daisy Chain

by providing a pulse to the next device when the previous

device reaches the last location of memory.

DATA OUTPUTS (Q0 – Q8)

Data outputs for 9-bit wide data. This data is in a high

impedance condition whenever Read (R) is in a high state.

t RSC

RS

t RS

t RSS

W

t RSS

R

t EFL

EF

HF, FF

t HFH, t FFH

NOTES:

1. EF, FF, HF may change status during Reset, but flags will be valid at tRSC.

2. W and R = VIH around the rising edge of RS.

Figure 2. Reset

t RSR

R

Q0 – Q8

W

D0 – D8

t RC

tA

t RR

t RPW

tA

t RLZ

t WPW

t DV

DATA OUT VALID

t WC

t WR

t RHZ

DATA OUT VALID

tDS

tDH

DATA IN VALID

DATA IN VALID

Figure 3. Asynchronous Write and Read Operation

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LAST WRITE IGNORED

WRITE

FIRST READ

ADDITIONAL FIRST

READS

WRITE

R

W

t WFF

FF

tRFF

Figure 4. Full Flag From Last Write to First Read

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