IDT723673L15PF 查看數據表（PDF） - Integrated Device Technology

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IDT723673L15PF

CMOS SyncFIFO™ WITH BUS-MATCHING 2,048 x 36 4,096 x 36 8,192 x 36

Integrated Device Technology 

IDT723653/723663/723673 CMOS SyncFIFOTM WITH BUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

Communication between each port may bypass the FIFO via two mailbox

registers. The mailbox registers' width matches the selected Port B bus width.

Each mailbox register has a flag (MBF1 and MBF2) to signal when new mail

has been stored.

Two kinds of reset are available on these FIFOs: Reset and Partial Reset.

Reset initializes the read and write pointers to the first location of the memory array

and selects serial flag programming, parallel flag programming, or one of five

possible default flag offset settings, 8, 16, 64, 256 or 1,024.

Partial Reset also sets the read and write pointers to the first location of the

memory. Unlike Reset, any settings existing prior to Partial Reset (i.e.,

programming method and partial flag default offsets) are retained. Partial Reset

is useful since it permits flushing of the FIFO memory without changing any

configuration settings.

The FIFO has Retransmit capability, a Retransmit is performed after four clock

cycles of CLKA and CLKB, by taking the Retransmit pin, RT LOW while the

Retransmit Mode pin, RTM is HIGH. When a Retransmit is performed the read

pointer is reset to the first memory location.

These devices have two modes of operation: In the IDT Standard mode, the

first word written to an empty FIFO is deposited into the memory array. A read

operation is required to access that word (along with all other words residing

in memory). In the First Word Fall Through mode (FWFT), the first word written

to an empty FIFO appears automatically on the outputs, no read operation

required (Nevertheless, accessing subsequent words does necessitate a

formal read request). The state of the BE/FWFT pin during Reset determines

the mode in use.

The FIFO has a combined Empty/Output Ready Flag (EF/OR ) and a

combined Full/Input Ready Flag (FF/IR). The EF and FF functions are selected

in the IDT Standard mode. EF indicates whether or not the FIFO memory is

empty. FF shows whether the memory is full or not. The IR and OR functions

are selected in the First Word Fall Through mode. IR indicates whether or not

the FIFO has available memory locations. OR shows whether the FIFO has data

available for reading or not. It marks the presence of valid data on the outputs.

The FIFO has a programmable Almost-Empty flag (AE) and a programmable

Almost-Full flag (AF). AE indicates when a selected number of words remain

in the FIFO memory. AF indicates when the FIFO contains more than a selected

number of words.

FF/IR and AF are two-stage synchronized to the port clock that writes data

into its array. EF/OR and AE are two-stage synchronized to the port clock that

reads data from its array. Programmable offsets for AE and AF are loaded in

parallel using Port A or in serial via the SD input. Five default offset settings are

also provided. The AE threshold can be set at 8, 16, 64, 256 or 1,024 locations

from the empty boundary and the AF threshold can be set at 8, 16, 64, 256 or

1,024 locations from the full boundary. All these choices are made using the FS0,

FS1 and FS2 inputs during Reset.

Interspersed Parity is available and can be selected during a Master Reset

of the FIFO. If Interspersed Parity is selected then during parallel programming

of the flag offset values, the device will ignore data line A8 . If Non-Interspersed

Parity is selected then data line A8 will become a valid bit.

Two or more devices may be used in parallel to create wider data paths. In

First Word Fall Through mode, more than one device may be connected in

series to create greater word depths. The addition of external components is

unnecessary.

If, at any time, the FIFO is not actively performing a function, the chip will

automatically power down. During the power down state, supply current

consumption (ICC) is at a minimum. Initiating any operation (by activating control

inputs) will immediately take the device out of the Power Down state.

The IDT723653/723663/723673 are characterized for operation from 0°C

to 70°C. Industrial temperature range (-40°C to +85°C) is available by special

order. They are fabricated using IDT’s high speed, submicron CMOS technol-

ogy.

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