IDT72T36125 查看數據表（PDF） - Integrated Device Technology

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IDT72T36125

2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS

Integrated Device Technology 

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync 36-BIT FIFO

1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PIN DESCRIPTION (CONTINUED)

Symbol Name

I/O TYPE

Description

WHSTL(1) Write Port HSTL

Select

Vcc

+2.5v Supply

GND Ground Pin

Vref

Reference

Voltage

VDDQ O/P Rail Voltage

LVTTL

INPUT

I

I

I

I

This pin is used to select HSTL or 2.5V LVTTL inputs for the FIFO. If HSTL inputs are required, this input must

be tied HIGH. Otherwise it should be tied LOW.

These are Vcc supply inputs and must be connected to the 2.5V supply rail.

These are Ground pins an dmust be connected to the GND rail.

This is a Voltage Reference input and must be connected to a voltage level determined from the table,

“Recommended DC Operating Conditions”. This provides the reference voltage when using HSTL class

inputs. If HSTL class inputs are not being used, this pin should be tied LOW.

This pin should be tied to the desired voltage rail for providing power to the output drivers.

NOTES:

1. Inputs should not change state after Master Reset.

2. These pins are for the JTAG port. Please refer to pages 31-34 and Figures 6-8.

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