IDT72V3611(2014) 查看數據表（PDF） - Integrated Device Technology
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IDT72V3611 Datasheet PDF : 19 Pages
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IDT72V3611 3.3V, CMOS SyncFIFOTM
64 x 36
COMMERCIAL TEMPERATURE RANGE
SYNCHRONIZED FIFO FLAGS
Each FIFO flag is synchronized to its port clock through two flip-flop stages.
This is done to improve the flags’ reliability by reducing the probability of
metastable events on their outputs when CLKA and CLKB operate asynchro-
nously to one another. FF and AF are synchronized to CLKA. EF and AE are
synchronized to CLKB. Table 4 shows the relationship of the flags to the level
of FIFO fill.
EMPTY FLAG ( EF )
The FIFO Empty Flag is synchronized to the port clock that reads data from
its array (CLKB). When the EF is HIGH, new data can be read to the FIFO output
register. When the EF is LOW, the FIFO is empty and attempted FIFO reads
are ignored.
The FIFO read pointer is incremented each time a new word is clocked
to its output register. The state machine that controls an EF monitors a write
pointer and read pointer comparator that indicates when the FIFO memory
status is empty, empty+1, or empty+2. A word written to the FIFO can be read
to the FIFO output register in a minimum of three port-B clock (CLKB) cycles.
Therefore, an EF is LOW if a word in memory is the next data to be sent to the
FIFO output register and two CLKB cycles have not elapsed since the time the
word was written. The EF of the FIFO is set HIGH by the second LOW-to-HIGH
transition of CLKB, and the new data word can be read to the FIFO output
register in the following cycle.
A LOW-to-HIGH transition on CLKB begins the first synchronized cycle of
a write if the clock transition occurs at time tSKEW1 or greater after the write.
Otherwise, the subsequent CLKB cycle can be the first synchronization cycle
(see Figure 5).
FULL FLAG ( FF )
The FIFO Full Flag is synchronized to the port clock that writes data to its
array (CLKA). When the FF is HIGH, a FIFO memory location is free to receive
new data. No memory locations are free when the FF is LOW and attempted
writes to the FIFO are ignored.
Each time a word is written to the FIFO, its write pointer is incremented. The
state machine that controls the FF monitors a write pointer and read pointer
comparator that indicates when the FIFO memory status is full, full-1, or full-2.
From the time a word is read from the FIFO, its previous memory location is
ready to be written in a minimum of three port-A clock cycles. Therefore, a FF
is LOW if less than two CLKA cycles have elapsed since the next memory write
location has been read. The second LOW-to-HIGH transition on CLKA after
TABLE 4 – FIFO FLAG OPERATION
Synchronized Synchronized
Number of Words
to CLKB
to CLKA
in the FIFO
EF
AE
AF
FF
0
L
L
H
H
1 to X
H
L
H
H
(X+1) to [64-(X+1)]
H
H
H
H
(64-X) to 63
H
H
L
H
64
H
H
L
L
NOTE:
1. X is the value in the Almost-Empty flag and Almost-Full flag register.
the read sets the FF HIGH and data can be written in the following clock cycle.
A LOW-to-HIGH transition on CLKA begins the first synchronization cycle
of a read if the clock transition occurs at time tSKEW1 or greater after the read.
Otherwise, the subsequent clock cycle can be the first synchronization cycle (see
Figure 6).
ALMOST-EMPTY FLAG ( AE )
The FIFO Almost-Empty flag is synchronized to the port clock that reads
data from its array (CLKB). The state machine that controls the AE flag monitors
a write pointer and read pointer comparator that indicates when the FIFO
memory status is almost-empty, almost-empty+1, or almost-empty+2. The
almost-empty state is defined by the value of the Almost-Full and Almost-Empty
Offset register (X). This register is loaded with one of four preset values during
a device reset (see the Reset section). The AE flag is LOW when the FIFO
contains X or less words in memory and is HIGH when the FIFO contains (X+1)
or more words.
Two LOW-to-HIGH transitions on the port-B clock (CLKB) are required
after a FIFO write for the AE flag to reflect the new level of fill. Therefore, the
AE flag of a FIFO containing (X+1) or more words remains LOW if two CLKB
cycles have not elapsed since the write that filled the memory to the (X+1) level.
The AE flag is set HIGH by the second CLKB LOW-to-HIGH transition after the
FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH transition on
CLKB begins the first synchronization cycle if it occurs at time tSKEW2 or greater
after the write that fills the FIFO to (X+1) words. Otherwise, the subsequent CLKB
cycle can be the first synchronization cycle (see Figure 7).
ALMOST-FULL FLAG ( AF )
The FIFO Almost-Full flag is synchronized to the port clock that writes
data to its array (CLKA). The state machine that controls an AF flag monitors
a write pointer and read pointer comparator that indicates when the FIFO
memory status is almost-full, almost- full-1, or almost-full-2. The almost-full state
is defined by the value of the Almost-Full and Almost-Empty Offset register (X).
This register is loaded with one of four preset values during a device reset (see
the Reset section). The AF flag is LOW when the FIFO contains (64-X) or more
words in memory and is HIGH when the FIFO contains [64-(X+1)] or less words.
Two LOW-to-HIGH transitions on the port-A clock (CLKA) are required
after a FIFO read for the AF flag to reflect the new level of fill. Therefore, the
AF flag of a FIFO containing [64-(X+1)] or less words remains LOW if two CLKA
cycles have not elapsed since the read that reduced the number of words in
memory to [64-(X+1)]. The AF flag is set HIGH by the second CLKA LOW-to-
HIGH transition after the FIFO read that reduces the number of words in memory
to [64-(X+1)]. A LOW-to-HIGH transition on CLKA begins the first synchroni-
zation cycle if it occurs at time tSKEW2 or greater after the read that reduces the
number of words in memory to [64-(X+1)]. Otherwise, the subsequent CLKA
cycle can be the first synchronization cycle (see Figure 8).
MAILBOX REGISTERS
Two 36-bit bypass registers are on the IDT72V3611 to pass command and
control information between port A and port B. The Mailbox select (MBA, MBB)
inputs choose between a mail register and a FIFO for a port data transfer
operation. A LOW-to-HIGH transition on CLKA writes A0-A35 data to the mail1
register when port-A write is selected by CSA, W/RA, and ENA with MBA HIGH.
A LOW-to-HIGH transition on CLKB writes B0-B35 data to the mail2 register
when port-B write is selected by CSB, W/RB, and ENB with MBB HIGH. Writing
data to a mail register sets its corresponding flag (MBF1 or MBF2) LOW.
Attempted writes to a mail register are ignored while its mail flag is LOW.
When the port-B data (B0-B35) outputs are active, the data on the bus
comes from the FIFO output register when the port-B Mailbox select (MBB) input
10
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