IDT72V3611(2014) 查看數據表（PDF） - Integrated Device Technology
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IDT72V3611 Datasheet PDF : 19 Pages
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IDT72V3611 3.3V, CMOS SyncFIFOTM
64 x 36
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30 pF
Symbol
Parameter
IDT72V3611L15
Min.
Max.
Unit
fS
tA
tWFF
tREF
tPAE
tPAF
tPMF
tPMR
tMDV
tPDPE
tPOPE
tPOPB(3)
tPEPE
tPEPB(3)
tRSF
tEN
tDIS
Clock Frequency, CLKA or CLKB
Access Time, CLKB↑ to B0-B35
Propagation Delay Time, CLKA↑ to FF
Propagation Delay Time, CLKB↑ to EF
Propagation Delay Time, CLKB↑ to AE
Propagation Delay Time, CLKA↑ to AF
Propagation Delay Time, CLKA↑ to MBF1 LOW or
MBF2 HIGH and CLKB↑ to MBF2 LOW or MBF1 HIGH
Propagation Delay Time, CLKA↑ to B0-B35(1) and CLKB↑ to A0-A35(2)
Propagation Delay Time, MBB to B0-B35 Valid
Propagation Delay Time, A0-A35 Valid to PEFA
Valid; B0-B35 Valid to PEFB Valid
Propagation Delay Time, ODD/EVEN to PEFA and PEFB
Propagation Delay Time, ODD/EVEN to Parity Bits
(A8, A17, A26, A35) and (B8, B17, B26, B35)
Propagation Delay Time, CSA, ENA, W/RA, MBA, or
PGA to PEFA; CSB, ENB, W/RB, MBB, or PGB to PEFB
Propagation Delay Time, CSA, ENA W/RA, MBA, or PGA to Parity Bits (A8, A17,
A26, A35); CSB, ENB, W/RB, MBB, or PGB to Parity Bits (B8, B17, B26, B35)
Propagation Delay Time, RST to AE LOW and (AF, MBF1, MBF2) HIGH
Enable Time, CSA and W/RA LOW to A0-A35 Active
and CSB LOW and W/RB HIGH to B0-B35 Active
Disable Time, CSA or W/RA HIGH to A0-A35 at high impedance
and CSB HIGH or W/RB LOW to B0-B35 at high impedance
–
66.7
MHz
2
10
ns
2
10
ns
2
10
ns
2
10
ns
2
10
ns
1
9
ns
2
10
ns
1
10
ns
2
10
ns
2
10
ns
2
10
ns
1
10
ns
2
10
ns
1
15
ns
2
10
ns
1
9
ns
NOTES:
1. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.
2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
3. Only applies when reading data from a mail register.
8
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