IDT72V3611 查看數據表（PDF） - Integrated Device Technology
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IDT72V3611 Datasheet PDF : 20 Pages
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IDT72V3611 3.3V, CMOS SyncFIFOTM
64 x 36
PIN DESCRIPTION
COMMERCIAL TEMPERATURE RANGE
Symbol
A0-A35
AE
AF
Name
Port-A Data
Almost-Empty Flag
Almost-Full Flag
B0-B35
CLKA
Port-B Data.
Port-A Clock
CLKB
Port-B Clock
CSA
Port-A Chip Select
CSB
Port-B Chip Select
EF
Empty Flag
ENA
Port-A Enable
ENB
Port-B Enable
FF
Full Flag
FS1, FS0 Flag-OffsetSelects
MBA
Port-A Mailbox Select
MBB
Port-B Mailbox Select
MBF1
Mail1 Register Flag
MBF2
Mail2 Register Flag
ODD/
EVEN
PEFA
Odd/Even Parity
Select
Port-A Parity Error
Flag
I/O
I/O
O
O
I/O
I
I
I
I
O
I
I
O
I
I
I
O
O
I
O
[Port A)
Description
36-bit bidirectional data port for side A.
Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words
in the FIFO is less than or equal to the value in the offset register, X.
Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty
locations in the FIFO is less than or equal to the value in the Offset register, X.
36-bit bidirectional data port for side B.
CLKA is a continuous clock that synchronizes all data transfers through port-A and can be
asynchronous or coincident to CLKB. FF and AF are synchronized to the LOW-to-HIGH
transition of CLKA.
CLKB is a continuous clock that synchronizes all data transfers through port-B and can be
asynchronous or coincident to CLKA. EF and AE are synchronized totheLOW-to-HIGH
transition of CLKB.
CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port-A.
The A0-A35 outputs are in the high-impedance state when CSA is HIGH.
CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port-B.
The B0-B35 outputs are in the high-impedance state when CSB is HIGH.
EF is synchronized to the LOW-to-HIGH transition of CLKB. When EF is LOW, the FIFO is empty,
and reads from its memory are disabled. Data can be read from the FIFO to its output register
when EF is HIGH. EF is forced LOW when the device is reset and is set HIGH by the second
LOW-to-HIGH transition of CLKB after data is loaded into empty FIFO memory.
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port-A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port-B.
FF is synchronized to the LOW-to-HIGH transition of CLKA. When FF is LOW, the FIFO is full, and
writes to its memory are disabled. FF is forced LOW when the device is reset and is set HIGH by
the second LOW-to-HIGH transition of CLKA after reset.
The LOW-to-HIGH transition of RST latches the values of FS0 and FS1, which loads one of four
preset values into the Almost-Full and Almost-Empty Offset register (X).
A HIGH level on MBA chooses a mailbox register for a port-A read or write operation.
A HIGH level on MBB chooses a mailbox register for a port-B read or write operation. When the
B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register for output,
and a LOW level selects the FIFO output register data for output.
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes
to the mail1 register are inhibited while MBF1 is set LOW. MBF1 is set HIGH by a LOW-to-HIGH
transition of CLKB when a port-B read is selected and MBB is HIGH. MBF1 is set HIGH when the
device is reset.
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes
to the mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH
transition of CLKA when a port-A read is selected and MBA is HIGH. MBF2 is set HIGH when the
device is reset.
Odd parity is checked on each port when ODD/EVEN is HIGH, and even parity is checked when
ODD/EVEN is LOW. ODD/EVEN also selects the type of parity generated for each port if parity
generation is enabled for a read operation.
When any byte applied to terminals A0-A35 fails parity, PEFA is LOW. Bytes are organized as
A0-A8, A9-A17, A18-A26, and A27-A35, with the most significant bit of each byte serving as the
parity bit. The type of parity checked is determined by the state of the ODD/EVEN input. The
parity trees used to check the A0-A35 inputs are shared by the mail2 register to generate parity if
parity generation is selected by PGA. Therefore, if a mail2 read with parity generation is setup by
having CSA LOW, ENA HIGH, W/RA LOW, MBA HIGH, and PGA HIGH, the PEFA flag is forced
HIGH regardless of the state of A0-A35 inputs.
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