IDT72V3611 查看數據表（PDF） - Integrated Device Technology

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IDT72V3611

3.3 VOLT CMOS SyncFIFO 64 x 36

Integrated Device Technology 

IDT72V3611 3.3V, CMOS SyncFIFOTM

64 x 36

PIN DESCRIPTION (CONTINUED)

COMMERCIAL TEMPERATURE RANGE

Symbol

PEFB

Name

Port-B Parity Error

Flag

PGA Port-A Parity

Generation

PGB Port-B Parity

Generation

RST

Reset

W/RA

W/RB

Port-A Write/Read

Select

Port-B Write/Read

Select

I/O

O

(Port B)

I

I

I

I

I

Description

When any byte applied to terminals B0-B35 fails parity, PEFB is LOW. Bytes are organized as

B0-B8, B9-B17, B18-B26, B27-B35, with the most significant bit of each byte serving as the parity

bit. The type of parity checked is determined by the state of the ODD/EVEN input. The parity

trees used to check the B0-B35 inputs are shared by the mail1 register to generate parity if parity

generation is selected by PGB. Therefore, if a mail1 read with parity generation is setup by

having CSB LOW, ENB HIGH, W/RB LOW, MBB HIGH, and PGB HIGH, the PEFB flag is forced

HIGH regardless of the state of the B0-B35 inputs

Parity is generated for mail2 register reads from port A when PGA is HIGH. The type of parity

generated is selected by the state of the ODD/EVEN input. Bytes are organized as A0-A8,

A9-A17, A18-A26, and A27-A35. The generated parity bits are output in the most significant bit

of each byte.

Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated

is selected by the state of the ODD/EVEN input. Bytes are organized as B0-B8, B9-B17,

B18-B26, and B27-B35. The generated parity bits areoutputinthemostsignificantbitof

each byte.

To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of

CLKB must occur while RST is LOW. This sets the AF, MBF1, and MBF2 flags HIGH and the

EF, AE, and FF flags LOW. The LOW-to-HIGH transition of RST latches the status of the FS1

and FS0 inputs to select Almost-Full and Almost-Empty flag offset.

A HIGH selects a write operation and a LOW selects a read operation on port A for a

LOW-to-HIGH transition of CLKA. The A0-A35 outputs are in the high-impedance state

when W/RA is HIGH.

A HIGH selects a write operation and a LOW selects a read operation on port B for a

LOW-to-HIGH transition of CLKB. The B0-B35 outputs are in the high-impedance state

when W/RB is HIGH.

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