IDT72V3611 查看數據表（PDF） - Integrated Device Technology
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IDT72V3611 Datasheet PDF : 20 Pages
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IDT72V3611 3.3V, CMOS SyncFIFOTM
64 x 36
COMMERCIAL TEMPERATURE RANGE
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURES
Symbol
Parameter
IDT72V3611L15
IDT72V3611L20
Min.
Max.
Min.
Max.
Unit
fS
Clock Frequency, CLKA or CLKB
–
66.7
–
50
Mhz
tCLK
Clock Cycle Time, CLKA or CLKB
15
–
20
–
Mhz
tCLKH
Pulse Duration, CLKA or CLKB HIGH
6
–
8
–
ns
tCLKL
Pulse Duration, CLKA or CLKB LOW
6
–
8
–
ns
tDS
Setup Time, A0-A35 before CLKA↑ and B0-B35
4
before CLKB↑
tENS1
CSA, W/RA, before CLKA↑; CSB, W/RB before CLKB↑
6
–
5
–
ns
–
6
–
ns
tENS2
tENS3
tPGS
tRSTS
tFSS
ENA before CLKA↑; ENB before CLKB↑
MBA before CLKA↑; ENB before CLKB↑
Setup Time, ODD/EVEN and PGB before CLKB↑(1)
Setup Time, RST LOW before CLKA↑ or CLKB↑(2)
Setup Time, FS0 and FS1 before RST HIGH
4
–
5
–
ns
4
–
5
–
ns
4
–
5
–
ns
5
–
6
–
ns
5
–
6
–
ns
tDH
Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑
1
tENH1
CSA, W/RA after CLKA↑; CSB, W/RB after CLKB↑
1
–
1
–
ns
–
1
–
ns
tENH2
ENA after CLKA↑; ENB after CLKB↑
1
1
ns
tENH3
tPGH
tRSTH
tFSH
MBA after CLKA↑; MBB after CLKB↑
Hold Time, ODD/EVEN and PGB after CLKB↑(1)
Hold Time, RST LOW after CLKA↑ or CLKB↑(2)
Hold Time, FS0 and FS1 after RST HIGH
1
1
ns
0
–
0
–
ns
6
–
6
–
ns
4
–
4
–
ns
tSKEW1(3)
Skew Time, between CLKA↑ and CLKB↑
for EF, FF
8
–
8
–
ns
tSKEW2(3,4) Skew Time, between CLKA↑ and CLKB↑
for AE, AF
14
–
16
–
ns
NOTES:
1. Only applies for a rising edge of CLKB that does a FIFO read.
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
4. Design simulated, not tested.
8
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