IDT72V3611 查看數據表（PDF） - Integrated Device Technology
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IDT72V3611 Datasheet PDF : 20 Pages
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IDT72V3611 3.3V, CMOS SyncFIFOTM
64 x 36
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30 pF
IDT72V3611L15
IDT72V3611L20
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
fS
Clock Frequency, CLKA or CLKB
–
66.7
–
50
MHz
tA
Access Time, CLKB↑ to B0-B35
2
10
2
12
ns
tWFF
Propagation Delay Time, CLKA↑ to FF
2
10
2
12
ns
tREF
Propagation Delay Time, CLKB↑ to EF
2
10
2
12
ns
tPAE
Propagation Delay Time, CLKB↑ to AE
2
10
2
12
ns
tPAF
Propagation Delay Time, CLKA↑ to AF
2
10
2
12
ns
tPMF
Propagation Delay Time, CLKA↑ to MBF1 LOW or
1
9
1
12
ns
MBF2 HIGH and CLKB↑ to MBF2 LOW or MBF1 HIGH
tPMR
Propagation Delay Time, CLKA↑ to B0-B35(1)
and CLKB↑ to A0-A35(2)
2
10
3
12
ns
tMDV
tPDPE
Propagation Delay Time, MBB to B0-B35 Valid
Propagation Delay Time, A0-A35 Valid to PEFA
Valid; B0-B35 Valid to PEFB Valid
1
10
1
11.5
ns
2
10
2
11
ns
tPOPE
Propagation Delay Time, ODD/EVEN to PEFA
and PEFB
2
10
2
12
ns
tPOPB(3)
Propagation Delay Time, ODD/EVEN to Parity
Bits (A8, A17, A26, A35) and (B8, B17, B26, B35)
2
10
2
12
ns
tPEPE
Propagation Delay Time, CSA, ENA, W/RA,
MBA, or PGA to PEFA; CSB, ENB, W/RB,
MBB, or PGB to PEFB
1
10
1
12
ns
tPEPB(3)
Propagation Delay Time, CSA, ENA W/RA,
MBA, or PGA to Parity Bits (A8, A17, A26,
A35); CSB, ENB, W/RB, MBB, or PGB to Parity
Bits (B8, B17, B26, B35)
2
10
2
12
ns
tRSF
Propagation Delay Time, RST to AE LOW and
(AF, MBF1, MBF2) HIGH
1
15
1
20
ns
tEN
Enable Time, CSA and W/RA LOW to A0-A35 Active
and CSB LOW and W/RB HIGH to B0-B35 Active
2
10
2
12
ns
tDIS
Disable Time, CSA or W/RA HIGH to A0-A35
at high impedance and CSB HIGH or W/RB
LOW to B0-B35 at high impedance
1
9
1
10
ns
NOTES:
1. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.
2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
3. Only applies when reading data from a mail register.
9
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