IDT72V801 查看數據表（PDF） - Integrated Device Technology
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IDT72V801 Datasheet PDF : 16 Pages
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IDT72V801/72V811/72V821/72V831/72V841/72V851
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
RCLKA (RCLKB)
tENS
RENA1, RENA2
(RENB1, RENB2)
EFA (EFB)
QA0 - QA8
(QB0 - QB8)
OEA (OEB)
WCLKA, WCLKB
tCLKH
tCLK
tCLKL
tENH
tREF
NO OPERATION
tOLZ
tA
tOE
VALID DATA
tOHZ
tSKEW1(1)
tREF
WENA1 (WENB1)
WENA2 (WENB2)
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NOTE:
1. tSKEW1 is the minimum time between a rising WCLKA (WCLKB) edge and a rising RCLKA (RCLKB) edge for EFA (EFB) to change during the current clock cycle. If the time
between the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW1, then EFA (EFB) may not change state until the next RCLKA (RCLKB)
edge.
Figure 6. Read Cycle Timing
WCLKA
(WCLKB)
DA0 - DA8
(DB0 - DB8)
WENA1
(WENB1)
WENA2 (WENB2)
(If Applicable)
RCLKA
(RCLKB)
EFA (EFB)
tDS
tENS
tENS
tSKEW1
D1
D0 (First Valid
tFRL(1)
tREF
RENA1, RENA2
(RENB1, RENB2)
QA0 - QA8
(QB0 - QB8)
OEA (OEB)
tENS
tOLZ
tA
tOE
NOTE:
1. When tSKEW1 ≥ minimum specification, tFRL = tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timings apply only at the Empty Boundary (EFA, EFB = LOW).
Figure 7. First Data Word Latency Timing
10
D2
D3
tA
D0
D1
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