IDT72V36102 查看數據表（PDF） - Integrated Device Technology
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IDT72V36102 Datasheet PDF : 29 Pages
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IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFOTM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
CLKA
CLKB
RST1
tRSTS
FWFT
COMMERCIAL TEMPERATURE RANGE
tFSS
tRSTH
tFSH
tFWS
FS1,FS0
FFA/IRA
EFB/ORB
AEB
AFA
MBF1
tPIR
tPRF
tPRF
tPRF
0,1
tPOR
NOTES:
1. FIFO2 is reset in the same manner to load X2 and Y2 with a preset value.
2. If FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than in this case where FWFT is LOW.
tPIR
4679 drw 05
Figure 2. FIFO1 Reset and Loading X1 and Y1 with a Preset Value of Eight(1) (IDT Standard and FWFT Modes)
CLKA
4
1
2
tFSS
RST1,
RST2
tFSH
FS1,FS0
0,0
FFA/IRA
tPIR
tENS2
tENH
tSKEW1(1)
ENA
A0 - A35
tDH
tDS
AFA Offset
(Y1)
AEB Offset
(X1)
AFB Offset
(Y2)
AEA Offset
(X2)
First Word to FIFO1
CLKB
1
2
FFB/IRB
tPIR
4679 drw 06
NOTES:
1. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB edge for FFB/IRB to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising
edge of CLKB is less than tSKEW1, then FFB/IRB may transition HIGH one CLKB cycle later than shown.
2. CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program offset register on consecutive clock cycles.
Figure 3. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset
(IDT Standard and FWFT Modes)
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