IDT72V36102 查看數據表（PDF） - Integrated Device Technology

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IDT72V36102

3.3 VOLT CMOS SyncBiFIFO

Integrated Device Technology 

IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFOTM

16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2

CLKB

CSB LOW

W/RB

MBB

ENB

LOW

tENS2

tENS2

tENH

tENH

tCLK

tCLKH tCLKL

COMMERCIAL TEMPERATURE RANGE

FFB

B0-B35

CLKA

HIGH

tDS

tDH

W1

(1)

tSKEW1

tCLK

tCLKH tCLKL

1

EFA FIFO2 Empty

2

tPOR

tPOR

CSA

W/RA

LOW

LOW

MBA LOW

ENA

tENS2

tENH

A0-A35

tA

W1

4679 drw 14

NOTE:

1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising

CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.

Figure 11. EFA Flag Timing and First Data Read when FIFO2 is Empty (IDT Standard Mode)

20

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