IDT82V2081(2019) 查看數據表（PDF） - Integrated Device Technology

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IDT82V2081
(Rev.:2019)

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Integrated Device Technology 

IDT82V2081

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

2 PIN DESCRIPTION

Table-1 Pin Description

Name

TTIP

TRING

RTIP

RRING

TD/TDP

TDN

Type

Analog

output

Analog

input

I

TQFP 44 QFN 48

Pin No. Pin No.

Description

37

40 TTIP/TRING: Transmit Bipolar Tip/Ring

36

39 These pins are the differential line driver outputs. They will be in high impedance state under the following conditions:

• THZ pin is high;

• THZ bit is set to 1;

• Loss of MCLK;

• Loss of TCLK (exceptions: Remote Loopback; transmit internal pattern by MCLK);

• Transmit path power down;

• After software reset; pin reset and power on.

41

44 RTIP/RRING: Receive Bipolar Tip/Ring

40

43 These signals are the differential receiver inputs.

2

2 TD: Transmit Data

3

3 When the device is in single rail mode, the NRZ data to be transmitted is input on this pin. Data on TD pin is sampled into

the device on the active edge of TCLK and is encoded by AMI, HDB3 or B8ZS line code rules before being transmitted.

In this mode, TDN should be connected to ground.

TDP/TDN: Positive/Negative Transmit Data

When the device is in dual rail mode, the NRZ data to be transmitted for positive/negative pulse is input on these pins.

Data on TDP/TDN pin is sampled into the device on the active edge of TCLK. The line code in dual rail mode is as follows:

TCLK

I

RD/RDP

O

CV/RDN

TDP

TDN

Output Pulse

0

0

Space

0

1

Positive Pulse

1

0

Negative Pulse

1

1

Space

1

1 TCLK: Transmit Clock input

This pin inputs 1.544 MHz for T1/J1 mode or 2.048 MHz for E1 mode transmit clock. The transmit data at TD/TDP or TDN

is sampled into the device on the active edge of TCLK. If TCLK is missing1 and the TCLK missing interrupt is not masked,

an interrupt will be generated.

5

5 RD: Receive Data output

6

6 In single rail mode, this pin outputs NRZ data. The data is decoded according to AMI, HDB3 or B8ZS line code rules.

CV: Code Violation indication

In single rail mode, the BPV/CV code violation will be reported by driving the CV pin to high level for a full clock cycle.

B8ZS/HDB3 line code violation can be indicated if the B8ZS/HDB3 decoder is enabled. When AMI decoder is selected,

bipolar violation will be indicated.

In hardware control mode, the EXZ, BPV/CV errors in received data stream are always monitored by the CV pin if single

rail mode is chosen.

RDP/RDN: Positive/Negative Receive Data output

In dual rail mode, this pin outputs the re-timed NRZ data when CDR is enabled, or directly outputs the raw RZ slicer data

if CDR is bypassed.

Active edge and level select:

Data on RDP/RDN or RD is clocked with either the rising or the falling edge of RCLK. The active polarity is also selectable.

Notes:

1. TCLK missing: the state of TCLK continues to be high level or low level over 70 MCLK cycles.

Pin Description

10

January 7, 2019

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