IDT82V3002A 查看數據表（PDF） - Integrated Device Technology

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IDT82V3002A

WAN PLL WITH DUAL REFERENCE INPUTS

Integrated Device Technology 

IDT82V3002A WAN PLL WITH DUAL REFERENCE INPUTS

INDUSTRIAL TEMPERATURE RANGE

LIST OF FIGURES

Figure - 1 Block Diagram .................................................................................................................................................. 2

Figure - 2 IDT82V3002A SSOP56 Package Pin Assignment........................................................................................... 6

Figure - 3 State Control Block......................................................................................................................................... 10

Figure - 4 State Control Diagram.................................................................................................................................... 11

Figure - 5 TIE Control Circuit Diagram ........................................................................................................................... 13

Figure - 6 Reference Switch with TIE Control Block Enabled......................................................................................... 13

Figure - 7 Reference Switch with TIE Control Block Disabled........................................................................................ 14

Figure - 8 DPLL Block Diagram ...................................................................................................................................... 15

Figure - 9 Clock Oscillator Circuit ................................................................................................................................... 16

Figure - 10 Power-Up Reset Circuit.................................................................................................................................. 16

Figure - 11 Input to Output Timing (Normal Mode)........................................................................................................... 25

Figure - 12 Output Timing 1.............................................................................................................................................. 26

Figure - 13 Output Timing 2.............................................................................................................................................. 27

Figure - 14 Input Control Setup and Hold Timing ............................................................................................................. 27

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