IDT82V3352 查看數據表（PDF） - Integrated Device Technology

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IDT82V3352

SYNCHRONOUS ETHERNET WAN PLL

Integrated Device Technology 

Table of Contents

FEATURES .............................................................................................................................................................................. 7

HIGHLIGHTS.................................................................................................................................................................................................... 7

MAIN FEATURES ............................................................................................................................................................................................ 7

OTHER FEATURES ......................................................................................................................................................................................... 7

APPLICATIONS....................................................................................................................................................................... 7

DESCRIPTION......................................................................................................................................................................... 8

FUNCTIONAL BLOCK DIAGRAM .......................................................................................................................................... 9

1 PIN ASSIGNMENT ........................................................................................................................................................... 10

2 PIN DESCRIPTION .......................................................................................................................................................... 11

3 FUNCTIONAL DESCRIPTION ......................................................................................................................................... 15

3.1 RESET ........................................................................................................................................................................................................... 15

3.2 MASTER CLOCK .......................................................................................................................................................................................... 15

3.3 INPUT CLOCKS & FRAME SYNC SIGNALS ............................................................................................................................................... 16

3.3.1 Input Clocks .................................................................................................................................................................................... 16

3.3.2 Frame SYNC Input Signals ............................................................................................................................................................ 16

3.4 INPUT CLOCK PRE-DIVIDER ...................................................................................................................................................................... 17

3.5 INPUT CLOCK QUALITY MONITORING ..................................................................................................................................................... 18

3.5.1 Activity Monitoring ......................................................................................................................................................................... 18

3.5.2 Frequency Monitoring ................................................................................................................................................................... 19

3.6 DPLL INPUT CLOCK SELECTION .............................................................................................................................................................. 20

3.6.1 External Fast Selection .................................................................................................................................................................. 20

3.6.2 Forced Selection ............................................................................................................................................................................ 21

3.6.3 Automatic Selection ....................................................................................................................................................................... 21

3.7 SELECTED INPUT CLOCK MONITORING .................................................................................................................................................. 22

3.7.1 DPLL Locking Detection ................................................................................................................................................................ 22

3.7.1.1 Fast Loss .......................................................................................................................................................................... 22

3.7.1.2 Coarse Phase Loss .......................................................................................................................................................... 22

3.7.1.3 Fine Phase Loss ............................................................................................................................................................... 22

3.7.1.4 Hard Limit Exceeding ....................................................................................................................................................... 22

3.7.2 Locking Status ............................................................................................................................................................................... 22

3.7.3 Phase Lock Alarm .......................................................................................................................................................................... 22

3.8 SELECTED INPUT CLOCK SWITCH ........................................................................................................................................................... 24

3.8.1 Input Clock Validity ........................................................................................................................................................................ 24

3.8.2 Selected Input Clock Switch ......................................................................................................................................................... 24

3.8.2.1 Revertive Switch ............................................................................................................................................................... 24

3.8.2.2 Non-Revertive Switch ....................................................................................................................................................... 24

3.8.3 Selected / Qualified Input Clocks Indication ................................................................................................................................ 24

3.9 SELECTED INPUT CLOCK STATUS VS. DPLL OPERATING MODE ....................................................................................................... 26

3.9.1 T0 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 26

3.10 DPLL OPERATING MODE ........................................................................................................................................................................... 28

3.10.1 T0 DPLL Operating Mode .............................................................................................................................................................. 28

3.10.1.1 Free-Run Mode ................................................................................................................................................................ 28

3.10.1.2 Pre-Locked Mode ............................................................................................................................................................. 28

3.10.1.3 Locked Mode .................................................................................................................................................................... 28

3.10.1.3.1 Temp-Holdover Mode .................................................................................................................................... 28

3.10.1.4 Lost-Phase Mode ............................................................................................................................................................. 28

3.10.1.5 Holdover Mode ................................................................................................................................................................. 28

Table of Contents

3

March 23, 2009

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