IDT82V3390 查看數據表（PDF） - Integrated Device Technology
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IDT82V3390 Datasheet PDF : 182 Pages
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IDT82V3390 DATASHEET
SYNCHRONOUS ETHERNET WAN PLL
3.10.1.3.1 Temp-Holdover Mode .................................................................................................................................... 35
3.10.1.4 Lost-Phase Mode ............................................................................................................................................................. 35
3.10.1.5 Holdover Mode ................................................................................................................................................................. 35
3.10.1.5.1 Automatic Instantaneous ............................................................................................................................... 36
3.10.1.5.2 Automatic Slow Averaged ............................................................................................................................. 36
3.10.1.5.3 Automatic Fast Averaged .............................................................................................................................. 36
3.10.1.5.4 Manual ........................................................................................................................................................... 36
3.10.1.5.5 Holdover Frequency Offset Read .................................................................................................................. 36
3.10.1.6 Pre-Locked2 Mode ........................................................................................................................................................... 36
3.10.2 T4 DPLL Operating Mode .............................................................................................................................................................. 36
3.10.2.1 Free-Run Mode ................................................................................................................................................................ 36
3.10.2.2 Locked Mode .................................................................................................................................................................... 36
3.10.2.3 Holdover Mode ................................................................................................................................................................. 36
3.11 T0 / T4 DPLL OUTPUT ................................................................................................................................................................................. 38
3.11.1 PFD Output Limit ............................................................................................................................................................................ 38
3.11.2 Frequency Offset Limit .................................................................................................................................................................. 38
3.11.3 Hitless Reference Switching (T0 only) ......................................................................................................................................... 38
3.11.4 Phase Offset Selection (T0 only) .................................................................................................................................................. 38
3.11.5 Five Paths of T0 / T4 DPLL Outputs ............................................................................................................................................. 38
3.11.5.1 T0 Path ............................................................................................................................................................................. 38
3.11.5.2 T4 Path ............................................................................................................................................................................. 38
3.12 T0 / T4 APLL ................................................................................................................................................................................................. 40
3.12.1 OPTIONAL EXTERNAL FILTER ..................................................................................................................................................... 40
3.13 OUTPUT CLOCKS & FRAME SYNC SIGNALS ........................................................................................................................................... 41
3.13.1 Output Clocks ................................................................................................................................................................................. 41
3.13.2 Frame SYNC Output Signals ......................................................................................................................................................... 43
3.14 MASTER / SLAVE CONFIGURATION ......................................................................................................................................................... 45
3.15 INTERRUPT SUMMARY ............................................................................................................................................................................... 46
3.16 T0 AND T4 SUMMARY ................................................................................................................................................................................. 46
3.17 POWER SUPPLY FILTERING TECHNIQUES ............................................................................................................................................. 47
4 TYPICAL APPLICATION ................................................................................................................................................. 48
4.1 MASTER / SLAVE APPLICATION ............................................................................................................................................................... 48
5 MICROPROCESSOR INTERFACE .................................................................................................................................. 49
5.1 EPROM MODE .............................................................................................................................................................................................. 51
5.2 MULTIPLEXED MODE .................................................................................................................................................................................. 52
5.3 INTEL MODE ................................................................................................................................................................................................. 55
5.4 MOTOROLA MODE ...................................................................................................................................................................................... 57
5.5 SERIAL MODE .............................................................................................................................................................................................. 59
5.6 I2C MODE ...................................................................................................................................................................................................... 61
5.6.1 I2C Device address ........................................................................................................................................................................ 61
5.6.2 I2C Bus Timing ............................................................................................................................................................................... 61
5.6.3 Supported Transactions ................................................................................................................................................................ 61
6 JTAG ................................................................................................................................................................................ 63
7 PROGRAMMING INFORMATION .................................................................................................................................... 64
7.1 REGISTER MAP ............................................................................................................................................................................................ 64
7.2 REGISTER DESCRIPTION ........................................................................................................................................................................... 70
7.2.1 Global Control Registers ............................................................................................................................................................... 70
7.2.2 Interrupt Registers ......................................................................................................................................................................... 79
7.2.3 Input Clock Frequency & Priority Configuration Registers ....................................................................................................... 84
7.2.4 Input Clock Quality Monitoring Configuration & Status Registers ......................................................................................... 107
7.2.5 T0 / T4 DPLL Input Clock Selection Registers ........................................................................................................................... 123
7.2.6 T0 / T4 DPLL State Machine Control Registers ......................................................................................................................... 127
7.2.7 T0 / T4 DPLL & APLL Configuration Registers .......................................................................................................................... 129
Datasheet
4
July 14, 2011
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