IDT82V3390 查看數據表（PDF） - Integrated Device Technology

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IDT82V3390

SYNCHRONOUS ETHERNET IDT WAN PLL™

Integrated Device Technology 

List of Tables

Datasheet

Table 1: Pin Description ............................................................................................................................................................................................. 13

Table 2: Related Bit / Register in Chapter 3.2 ........................................................................................................................................................... 19

Table 3: Related Bit / Register in Chapter 3.3 ........................................................................................................................................................... 20

Table 4: Pre-Divider Function .................................................................................................................................................................................... 22

Table 5: Related Bit / Register in Chapter 3.5 ........................................................................................................................................................... 25

Table 6: Input Clock Selection for T0 Path ................................................................................................................................................................ 26

Table 7: Input Clock Selection for T4 Path ................................................................................................................................................................ 26

Table 8: External Fast Selection ................................................................................................................................................................................ 26

Table 9: Related Bit / Register in Chapter 3.6 ........................................................................................................................................................... 27

Table 10: Coarse Phase Limit Programming (the selected input clock of 2 kHz, 4 kHz or 8 kHz) .............................................................................. 28

Table 11: Coarse Phase Limit Programming (the selected input clock of other than 2 kHz, 4 kHz and 8 kHz) .......................................................... 28

Table 12: Related Bit / Register in Chapter 3.7 ........................................................................................................................................................... 29

Table 13: Conditions of Qualified Input Clocks Available for T0 & T4 Selection ......................................................................................................... 30

Table 14: Related Bit / Register in Chapter 3.8 ........................................................................................................................................................... 31

Table 15: T0 DPLL Operating Mode Control ............................................................................................................................................................... 32

Table 16: T4 DPLL Operating Mode Control ............................................................................................................................................................... 34

Table 17: Related Bit / Register in Chapter 3.9 ........................................................................................................................................................... 34

Table 18: Frequency Offset Control in Temp-Holdover Mode ..................................................................................................................................... 35

Table 19: Frequency Offset Control in Holdover Mode ............................................................................................................................................... 36

Table 20: Holdover Frequency Offset Read ................................................................................................................................................................ 36

Table 21: Related Bit / Register in Chapter 3.10 ......................................................................................................................................................... 37

Table 22: Related Bit / Register in Chapter 3.11 ......................................................................................................................................................... 39

Table 23: Related Bit / Register in Chapter 3.12 ......................................................................................................................................................... 40

Table 24: T0 / T4 APLL Approximate Loop Bandwidth Selection ................................................................................................................................ 40

Table 25: Outputs on OUT1 ~ OUT7 if Derived from T0/T4 DPLL Outputs ................................................................................................................ 41

Table 26: Outputs on OUT1 ~ OUT7 if Derived from T0/T4 APLL1 ............................................................................................................................ 42

Table 27: Outputs on OUT8 & OUT9 ........................................................................................................................................................................... 42

Table 28: Synchronization Control ............................................................................................................................................................................... 43

Table 29: Related Bit / Register in Chapter 3.13 ......................................................................................................................................................... 44

Table 30: Device Master / Slave Control ..................................................................................................................................................................... 45

Table 31: Related Bit / Register in Chapter 3.15 ......................................................................................................................................................... 46

Table 32: Microprocessor Interface ............................................................................................................................................................................. 49

Table 33: Microprocessor Interface Pins ..................................................................................................................................................................... 50

Table 34: Access Timing Characteristics in EPROM Mode ......................................................................................................................................... 51

Table 35: Read Timing Characteristics in Multiplexed Mode ....................................................................................................................................... 52

Table 36: Write Timing Characteristics in Multiplexed Mode ....................................................................................................................................... 54

Table 37: Read Timing Characteristics in Intel Mode .................................................................................................................................................. 55

Table 38: Write Timing Characteristics in Intel Mode .................................................................................................................................................. 56

Table 39: Read Timing Characteristics in Motorola Mode ........................................................................................................................................... 57

Table 40: Write Timing Characteristics in Motorola Mode ........................................................................................................................................... 58

Table 41: Read Timing Characteristics in Serial Mode ................................................................................................................................................ 59

Table 42: Write Timing Characteristics in Serial Mode ................................................................................................................................................ 60

Table 43: Description of Timing Parameters of I2C Master Interface .......................................................................................................................... 61

Table 44: Description of I2C Slave Interface Supported Transactions ........................................................................................................................ 62

Table 45: JTAG Timing Characteristics ....................................................................................................................................................................... 63

Table 46: Register List and Map .................................................................................................................................................................................. 64

Table 47: Power Consumption and Maximum Junction Temperature ....................................................................................................................... 156

Table 48: Thermal Data ............................................................................................................................................................................................. 156

List of Tables

6

July 14, 2011

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