IDT82V3390 查看數據表（PDF） - Integrated Device Technology

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IDT82V3390

SYNCHRONOUS ETHERNET IDT WAN PLL™

Integrated Device Technology 

List of Figures

Datasheet

Figure 1. Functional Block Diagram ............................................................................................................................................................................ 11

Figure 2. Pin Assignment (Top View) .......................................................................................................................................................................... 12

Figure 3. Pre-Divider for An Input Clock ..................................................................................................................................................................... 22

Figure 4. Input Clock Activity Monitoring ..................................................................................................................................................................... 23

Figure 5. Hysteresis Frequency Monitoring ................................................................................................................................................................ 24

Figure 6. External Fast Selection ................................................................................................................................................................................ 26

Figure 7. Qualified Input Clocks for Automatic Selection ............................................................................................................................................ 27

Figure 8. T0 Selected Input Clock vs. DPLL Automatic Operating Mode ................................................................................................................... 33

Figure 9. T4 Selected Input Clock vs. DPLL Automatic Operating Mode ................................................................................................................... 34

Figure 10. APLL External Filter Components .............................................................................................................................................................. 40

Figure 11. On Target Frame Sync Input Signal Timing ............................................................................................................................................... 43

Figure 12. 0.5 UI Early Frame Sync Input Signal Timing ............................................................................................................................................. 43

Figure 13. 0.5 UI Late Frame Sync Input Signal Timing .............................................................................................................................................. 44

Figure 14. 1 UI Late Frame Sync Input Signal Timing ................................................................................................................................................. 44

Figure 15. Physical Connection Between Two Devices .............................................................................................................................................. 45

Figure 16. IDT82V3390 Power Decoupling Scheme ................................................................................................................................................... 47

Figure 17. Typical Application ...................................................................................................................................................................................... 48

Figure 18. EPROM Access Timing Diagram ............................................................................................................................................................... 51

Figure 19. Multiplexed Read Timing Diagram ............................................................................................................................................................. 52

Figure 20. Multiplexed Write Timing Diagram .............................................................................................................................................................. 53

Figure 21. Intel Read Timing Diagram ......................................................................................................................................................................... 55

Figure 22. Intel Write Timing Diagram ......................................................................................................................................................................... 56

Figure 23. Motorola Read Timing Diagram .................................................................................................................................................................. 57

Figure 24. Motorola Write Timing Diagram .................................................................................................................................................................. 58

Figure 25. Serial Read Timing Diagram (CLKE Asserted Low) ................................................................................................................................... 59

Figure 26. Serial Read Timing Diagram (CLKE Asserted High) .................................................................................................................................. 59

Figure 27. Serial Write Timing Diagram ....................................................................................................................................................................... 60

Figure 28. Definition of I2C Bus Timing ...................................................................................................................................................................... 61

Figure 29. I2C Slave Interface Supported Transactions ............................................................................................................................................. 61

Figure 30. JTAG Interface Timing Diagram ................................................................................................................................................................. 63

Figure 31. Assembly for Expose Pad thermal Release Path (Side View) ................................................................................................................. 157

Figure 32. 64 kHz + 8 kHz Signal Structure .............................................................................................................................................................. 159

Figure 33. 64 kHz + 8 kHz + 0.4 kHz Signal Structure .............................................................................................................................................. 159

Figure 34. 64 kHz + 8 kHz / 64 kHz + 8 kHz + 0.4 kHz Signal Input Level ................................................................................................................ 159

Figure 35. 64 kHz + 8 kHz / 64 kHz + 8 kHz + 0.4 kHz Signal Output Level ............................................................................................................. 159

Figure 36. AMI Input / Output Port Line Termination (Recommended) ..................................................................................................................... 160

Figure 37. Recommended PECL Input Port Line Termination .................................................................................................................................. 162

Figure 38. Recommended PECL Output Port Line Termination ................................................................................................................................ 162

Figure 39. Recommended LVDS Input Port Line Termination .................................................................................................................................. 164

Figure 40. Recommended LVDS Output Port Line Termination ................................................................................................................................ 164

Figure 41. Example of Single-Ended Signal to Drive Differential Input ..................................................................................................................... 165

Figure 42. Output Wander Generation (TDEV) ......................................................................................................................................................... 170

Figure 43. Output Wander Generation (MTIE) .......................................................................................................................................................... 170

Figure 44. Input / Output Clock Timing ...................................................................................................................................................................... 171

Figure 45. Output Clock Timing ................................................................................................................................................................................. 172

Figure 46. 100-Pin EQG Package Dimensions (a) (in Millimeters) ............................................................................................................................ 178

Figure 47. 100-Pin EQG Package Dimensions (b) (in Millimeters) ............................................................................................................................ 179

Figure 48. EQG100 Recommended Land Pattern with Exposed Pad (in Millimeters) .............................................................................................. 180

List of Figures

8

July 14, 2011

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