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IN24LC08 查看數據表(PDF) - Integral Corp.

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产品描述 (功能)
生产厂家
IN24LC08
INTE-ElectronicGRAL
Integral Corp. INTE-ElectronicGRAL
IN24LC08 Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
IN24LC04/08
Acknowledge
Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of
each byte. The master device must generate an extra clock pulse which is associated with this
acknowledge bit.
Note: The IN24LC04/08 does not generate any acknowledge bits if an internal programming cycle is in
progress
The device that acknowledges, has to pull down the SDA line during the acknowledge clock pulse
in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related
clock pulse. Of course, setup and hold times must be taken into account. A master must signal an
end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked
out of the slave. In this case, the slave must leave the data line HIGH to enable the master to
generate the STOP condition.
Figure 4. Data Transfer Sequence on the serial bus
BUS CHARACTERISTICS
Device Addressing and Operation
A control byte is the first byte received following the start condition from the master device. The
control byte consists of a four bit control code, for the IN24LC04/08 this is set as 1010 binary for
read and write operations. The next three bits of the control byte are the block select bits (B2, B1,
BO). B2 is a don't care for both the IN24LC04 and IN24LC08; B1 is a don't care for the IN24LC04.
They are used by the master device to select which of the two or four 256 word blocks of memory
are to be accessed. These bits are in effect the most significant bits of the word address.
The last bit of the control byte defines the operation to be performed. When set to one a read
operation is selected, when set to zero a write operation is selected. Following the start condition,
the IN24LC04/08 monitors the SDA bus checking the device type identifier being transmitted, upon
a 1010 code the slave device outputs an acknowledge signal on the SDA line. Depending on the
state of the R/W bit, the IN24LC04/ 08 will select a read or write operation.
Operation
Read
Write
Control Code
1010
1010
Block Select
Block Address
Block Address
R/W
1
0
5

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