IN24LC16 查看數據表（PDF） - Integral Corp.

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IN24LC16

16K SERIAL EEPROM WITH I2C BUS

Integral Corp. 

IN24LC16

FUNCTIONAL DESCRIPTION

The 24LC16B supports a Bi-directional 2-wire bus and data transmission protocol. A device that sends data

onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled

by a master device which generates the serial clock (SCL), controls the bus access, and generates the

START and STOP conditions, while the 24LC16B works as slave. Both, master and slave can operate as

transmitter or receiver but the master device determines which mode is activated.

BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus is not busy.

• During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the

data line while the clock line is HIGH will be interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been defined

Bus not Busy (A)

Both data and clock lines remain HIGH.

Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All

commands must be preceded by a START condition.

Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All

operations must be ended with a STOP condition.

Data Valid (D)

The state of the data line represents valid data when, after a START condition, the data line is stable for the

duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse

per bit of data.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of

the data bytes transferred between the START and STOP conditions is determined by the master device

and is theoretically unlimited, although only the last sixteen will be stored when doing a write operation.

When an overwrite does occur it will replace data in a first in first out fashion.

Acknowledge

Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each

byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit.

Note: The 24LC16B does not generate any acknowledge bits if an internal programming cycle is in

progress.

The device that acknowledges, has to pull down the SDA line during the acknowledge clock pulse in such a

way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into account. During reads, a master must signal an end of data

to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In

this case, the slave (24LC16B) will leave the data line HIGH to enable the master to generate the STOP

condition.

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

Device Addressing

A control byte is the first byte received following the start condition from the master device. The control byte

consists of a four bit control code, for the 24LC16B this is set as 1010 binary for read and write operations.

The next three bits of the control byte are the block select bits (B2, B1, B0). They are used by the master

device to select which of the eight 256 word blocks of memory are to be accessed. These bits are in effect

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