IN24LC16 查看數據表（PDF） - Integral Corp.

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IN24LC16

16K SERIAL EEPROM WITH I2C BUS

Integral Corp. 

IN24LC16

the three most significant bits of the word address. It should be noted that the protocol limits the size of the

memory to eight blocks of 256 words, therefore the protocol can support only one 24LC16B per system.

The last bit of the control byte defines the operation to be performed. When set to one a read operation is

selected, when set to zero a write operation is selected. Following the start condition, the 24LC16B monitors

the SDA bus checking the device type identifier being transmitted, upon a 1010 code the slave device

outputs an acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24LC16B will

select a read or write operation.

Operation Control Block Select R/W

Code

Read

1010

Block Address 1

Write

1010

Block Address 0

CONTROL BYTE ALLOCATION

WRITE OPERATION

Byte Write

Following the start condition from the master, the device code (4 bits), the block address (3 bits), and the

R/W bit which is a logic low is placed onto the bus by the master transmitter. This indicates to the addressed

slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during

the ninth clock cycle. Therefore the next byte transmitted by the master is the word address and will be

written into the address pointer of the 24LC16B. After receiving another acknowledge signal from the

24LC16B the master device will transmit the data word to be written into the addressed memory location.

The 24LC16B acknowledges again and the master generates a stop condition. This initiates the internal

write cycle, and during this time the 24LC16B will not generate acknowledge signals (Figure 4-1).

Page Write

The write control byte, word address and the first data byte are transmitted to the 24LC16B in the same way

as in a byte write. But instead of generating a stop condition the master transmits up to 16 data bytes to the

24LC16B which are temporarily stored in the on-chip page buffer and will be written into the memory after

the master has transmitted a stop condition. After the receipt of each word, the four lower order address

pointer bits are internally incremented by one. The higher order seven bits of the word address remains

constant. If the master should transmit more than 16 words prior to generating the stop condition, the

address counter will roll over and the previously received data will be overwritten. As with the byte write

operation, once the stop condition is received an internal write cycle will begin

Note: Page write operations are limited to writing bytes within a single physical page, regardless of the

number of bytes actually being written. Physical page boundaries start at addresses that are integer

multiples of the page buffer size (or ‘page size’) and end at addresses that are integer multiples of [page size

- 1]. If a page write command attempts to write across a physical page boundary, the result is that the data

wraps around to the beginning of the current page (overwriting data previously stored there), instead of

being written to the next page as might be expected. It is therefore necessary for the application software to

prevent page write operations that would attempt to cross a page boundary.

BYTE WRITE

6

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