IN16C01 查看數據表（PDF） - Integral Corp.

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IN16C01

16-BIT RISC MICROCONTROLLER

Integral Corp. 

IN16C01

As one can see in the figure the microcontroller consists of the following units:

• CPU core

• RAM

• PROM

• Timer system (counter/timer, watchdog timer)

• UART

• Synchronous serial interface (SSI)

• Parallel ports D, C

The IN16C01 is a synchronous VLSI with fully static operation, i.e. the microcontroller’s clock may be shut

off indefinitely without the device losing its state. Once the clock is restored the microcontroller will begin

executing as if there had been no interruption.

The current IN16C01 realisation is assumed to have the maximum clock frequency of 10 MHz.

2.1 CPU core

The brains of the IN16C01 is the CPU core.

Main CPU core features are:

• Stack oriented RISC architecture

• 24-bit address

• 16/32-data

• Modified Harvard architecture with independent

simultaneous access to the program and data

spaces

• Two data stacks of 8 sixteen-bit words each

• Sixteen 24 bit words for return stack

• Eight 24 bit words for address stack

• All instructions are executed in one or two clock

cycles

• Interrupt response of two clock cycles

• 16x16 multiply in one clock cycle

• Multiply-accumulate (with 38 bit accumulator) in

two clock cycles

• Divide operation support

The stack oriented architecture means that the

processed data are stored in a stack (the data stack).

Vast majority of the microcontroller’s instructions use

one or two top stack words as their operands. The

particular feature of the IN16C01 is that it has four

stacks: two stacks for data, a return stack and an

address stack. All the stacks can operate

simultaneously. The data stacks contain processed

data. The return stack contains 'return from

subroutine' addresses or variables addresses. The

address stack contains variables addresses.

Fig. 2.2. Block diagram of the CPU core

The block diagram of the CPU core is shown in fig. 2.2. As one can see from the figure,

the CPU contains the following units:

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