IN74ACT534N 查看數據表（PDF） - IK Semicon Co., Ltd

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IN74ACT534N

Octal 3-state inverting D flip-flop high-speed silicon-gate CMOS

IK Semicon Co., Ltd 

IN74ACT534

AC ELECTRICAL CHARACTERISTICS (VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=3.0 ns)

Symbol

Parameter

fmax Maximum Clock Frequency (Figure 1)

tPLH Propagation Delay, Clock to Q (Figure 1)

tPHL Propagation Delay, Clock to Q (Figure 1)

tPZH Propagation Delay, Output Enable to Q

(Figure 2)

tPZL Propagation Delay, Output Enable to Q

(Figure 2)

tPHZ Propagation Delay, Output Enable to Q

(Figure 2)

tPLZ Propagation Delay, Output Enable to Q

(Figure 2)

CIN Maximum Input Capacitance

Guaranteed Limits

25 °C

-40°C to 85°C Unit

Min Max Min Max

120

ns

2.5 11.5 2.0 12.5

ns

2.0 10.5 2.0 12.0

ns

2.5 12.0 2.0 12.5

ns

2.0 11.0 2.0 11.5

ns

1.5 12.5 1.0 13.5

ns

1.5 10.5 1.0 10.5

ns

4.5

4.5

pF

CPD Power Dissipation Capacitance

Typical @25°C,VCC=5.0 V

40

pF

TIMING REQUIREMENTS (VCC=5.0 V ± 10%, CL=50pF, Input tr=tf=3.0 ns)

Symbol

Parameter

tsu

Minimum Setup Time, Data to Clock

(Figure 3)

th

Minimum Hold Time, Clock to Data

(Figure 3)

tw

Minimum Pulse Width, Clock (Figure 1)

Guaranteed Limits

25 °C

-40°C to

Unit

85°C

3.5

4.0

ns

1.0

1.5

ns

3.5

3.5

ns

Rev. 00

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