IND331SK 查看數據表（PDF） - Unspecified
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IND331SK Datasheet PDF : 40 Pages
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Preliminary Data Sheet
INDT/R166B
INDT/R331B
Mode
1
2
3
4
5
INDT/R331B configurations
High-speed
Sideband
Low-speed
Sideband
Audio
X
X
X/–
–
X
X
–
–
–
X
X
X
X
X
X
Up to
VESA-/DTV-Mode
SXGA 24 color bits
UXGA 18 color bits
UXGA 18 color bits
720p (60fps)
1080i (30fps)
Table 1.2: INDT/R331B Video Configuration
Note: Implementation of video modes other than VESA or DTV/HDTV is possible. Special modes may need evaluation.
1.2 Pixel Interface
1.2.1 General Information
The pixel interface is designed to support direct interfacing to any digital graphics device with a parallel data port such as
graphic-cards/controllers, CCD cameras or flat panel TFT displays. With standard interface devices the data port can also
be adapted to systems with non-generic parallel interfaces such as DVI or LVDS/OpenLDI.
PX_CLK+
PX_CLK–
PX_D[47:0]
48
PX_HSYNC
PX_VSYNC
PX_DE
Video
Downstream
INDT
Transmitter
PX_CLK_IN
PX_CLK_OUT
Video
48
INDR
Receiver
PX_CLK
PX_D[47:0]
PX_HSYNC
PX_VSYNC
PX_DE
Figure 1.2: Pixel Interface
Signal
PX_D[47:0]
PX_CLK+
PX_CLK–
PX_CLK
PX_CLK_OUT
PC_CLK_IN
PX_HSYNC
PX_VSYNC
PX_DE
Tx1 Rx Description
IN OUT Configurable parallel pixel data interface
IN OUT Tx Pixel clock 24 – 161 MHz, diff + or single-ended
IN OUT Tx Pixel clock 24 – 161 MHz, diff –
OUT Rx Pixel clock 24 – 161 MHz
OUT Rx Pixel clock 24 – 161 MHz, de-jitter
IN Rx Pixel clock 24 – 161 MHz, de-jitter
IN OUT Pixel data framing – Horizontal sync pulse
IN OUT Pixel data framing – Vertical sync pulse
IN OUT Pixel data framing – Data enable
Table 1.3: Pixel Interface Signals
1 Configurable to 3.3V or 1.8V input levels via VREF-pin.
Date: 2005-03-14 Revision: 0.1
Page 4 of 40
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