FDS6670AS 查看數據表（PDF） - Richtek Technology

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FDS6670AS

6A, 24V, 600kHz Step-Down Converter with Synchronous Gate Driver

Richtek Technology 

RT8298

Location

CI N

CI N

CI N

COUT

COUT

COUT

COUT

Table 4. Suggested Capacitors for CIN and COUT

Component Supplier

Part No.

Capacitance (μF)

MURATA

GRM31CR61E106K

10

TDK

C3225X5R1E106K

10

TAIYO YUDEN

TMK316BJ106ML

10

MURATA

GRM31CR60J476M

47

TDK

C3225X5R0J476M

47

MURATA

GRM32ER71C226M

22

TDK

C3225X5R1C22M

22

Case Size

1206

1206

1206

1206

1210

1210

1210

For the input capacitor, two 10μF low ESR ceramic

capacitors are recommended. For the recommended

capacitor, please refer to Table 4 for more details.

The selection of COUT is determined by the required ESR

to minimize voltage ripple.

Moreover, the amount of bulk capacitance is also a key

for COUT selection to ensure that the control loop is stable.

Loop stability can be checked by viewing the load transient

response as described in a later section.

The output ripple, ΔVOUT , is determined by :

ΔVOUT

≤

ΔIL

⎡⎢⎣ESR +

1

8fCOUT

⎤

⎥⎦

The output ripple will be the highest at the maximum input

voltage since ΔIL increases with input voltage. Multiple

capacitors placed in parallel may be needed to meet the

ESR and RMS current handling requirement.

Higher values, lower cost ceramic capacitors are now

becoming available in smaller case sizes. Their high ripple

current, high voltage rating and low ESR make them ideal

for switching regulator applications. When a ceramic

capacitor is used at the input and the power is supplied

by a wall adapter through long wires, a load step at the

output can induce ringing at the input, VIN. This ringing

can couple to the output and be mistaken. A sudden inrush

of current through the long wires can potentially cause a

voltage spike at VIN large enough to damage the part.

Checking Transient Response

The regulator loop response can be checked by looking

at the load transient response. Switching regulators take

several cycles to respond to a step load change. When a

step load occurs, VOUT immediately shifts by an amount

equal to ΔILOAD x ESR also begins to charge or discharge

COUT generating a feedback error signal for the regulator

to return VOUT to its steady-state value. During this

recovery time, VOUT can be monitored for overshoot or

ringing that would indicate a stability problem.

Thermal Considerations

For continuous operation, do not exceed absolute

maximum junction temperature. The maximum power

dissipation depends on the thermal resistance of the IC

package, PCB layout, rate of surrounding airflow, and

difference between junction and ambient temperature. The

maximum power dissipation can be calculated by the

following formula :

PD(MAX) = (TJ(MAX) − TA) / θJA

where TJ(MAX) is the maximum junction temperature, TA is

the ambient temperature, and θJA is the junction to ambient

thermal resistance.

For recommended operating condition specifications of

the RT8298, the maximum junction temperature is 125°C.

The junction to ambient thermal resistance, θJA, is layout

dependent. For SOP-8 (Exposed Pad) package, the

thermal resistance, θJA, is 75°C/W on a standard JEDEC

51-7 four-layer thermal test board.

Copyright ©2011 Richtek Technology Corporation. All rights reserved.

www.richtek.com

14

is a registered trademark of Richtek Technology Corporation.

DS8298-01 November 2011

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