IRS20955PBF 查看數據表（PDF） - International Rectifier
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IRS20955PBF Datasheet PDF : 21 Pages
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VDD
CSD
Ct
VSS
Vth1
`
COMP1
Vth2
`
COMP2
OC
SQ
R
IRS20955(S)PbF
PRELIMINARY
UVLO(VB)
OC DET (H)
HV
LEVEL
SHIFT
FLOATING INPUT
HV
LEVEL
SHIFT
HV
LEVEL
SHIFT
FLOATING HIGH SIDE
LOW SIDE
UVLO(VCC)
PWM
SD
HO
DEAD TIME
LO
`
OC DET (L)
Figure 7. Shutdown Functional Block Diagram
Protection Control
The internal protection control block dictates the
operational mode-norma, or shutdown, using the
input of the CSD pin. The IC functions as expected
in the normal mode. In shutdown mode, the IC
forces LO and HO to output 0 V with respect to
COM and VS to turn off the power MOSFETs.
The CSD pin provides five functions.
1. Power up delay timer
2. Self-reset timer
3. Shutdown input
4. Latched protection configuration
5. Shutdown status output (host I/F)
Self Reset Protection
By putting a capacitor between CSD and VSS, the
IRS20955S can reset itself after entering shutdown
mode.
VDD
CSH
CSD
VB
IN
HO
Ct
VSS
VS
NC
NC
VREF
VCC
OCSET
LO
DT
COM
Figure 8. Self Reset Protection Configuration
Designing Ct
The timing capacitor, Ct, is used to program tRESET
and tSU.
• tRESET, is the amount of time that elapses
from when the IC enters shutdown mode to
the time when the IC resumes operation.
tRESET should be long enough to avoid over
heating the MOSFET from the repetitive
sequence of shutting down and resuming
operation during over current conditions. In
most of applications, the minimum
recommended time for tRESET is 0.1.
• tSU is the amount of time between powering
up the IC in shutdown mode to the moment
the IC releases shutdown to begin normal
operation.
The values chosen for tRESET and tSU will determine
the capacitance of Ct using the given equations:
Ct = tRESET ⋅ ICSD [F]
1.1⋅VDD
Ct = tSU ⋅ ICSD [F]
0.7 ⋅VDD
where ICSD = the charge/discharge current at the
CSD pin
VDD = the supply voltage with respect to VSS.
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