IS24C128B 查看數據表（PDF） - Integrated Silicon Solution

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IS24C128B

65/536-bit/32/768-bit 2-WIRE SERIAL CMOS EEPROM

Integrated Silicon Solution 

IS24C128B

Figure 11 DEEP SLEEP ENTRY/EXIT INITIATION

S

W

T

R

S

A

R

Device

I

T

T

O

T

SDA

Address E * Word Address(FFh) Word Address(FDh)

A

A

A

Data(5Ah)

P

A

Bus

C

C

C

C

Activity

K

K

K

K

M

S

B

L

S

B

M

S

B

R/W

* The slave does not provide an acknowledgement if the Deep Sleep Mode is enabled, and after stop, it begins to exit.

Figure 12 DEEP SLEEP Verification

S

T

A

R Device

T Address

SDA

Bus

Activity

M

S

B

RS

ET

AO

D* P

A

C

K

L

S

B

R/W

* The slave does not provide an acknowledgement if the Deep Sleep Mode is already enabled.

This command does not affect Deep Sleep.

Integrated Silicon Solution, Inc. — www.issi.com

11

Rev.  00F

09/18/09

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