IS25C16 查看數據表（PDF） - Integrated Silicon Solution

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IS25C16

8K-BIT/16K-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM

Integrated Silicon Solution 

IS25C08

IS25C16

ISSI ®

STATUS REGISTER

The status register contains 8-bits for write protection

control and write status. (See Table 1). It is the only

region of memory other than the main array that is

accessible by the user.

Table 1. Status Register Format

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0

WPEN X X X BP1 BP0 WEN RDY

Notes:

1. X = Don't care bit.

2. During internal write cycles, bits 0 to 7 are temporarily 1's.

The Status Register is Read-Only if either: a) Hardware

Write Protection is enabled or b) WEN is set to 0. If

neither is true, it can be modified by a valid instruction.

Ready (RDY), Bit 0: When RDY = 1, it indicates that

the device is busy with a write cycle. RDY = 0 indi-

cates that the device is ready for an instruction. If RDY

= 1, the only command that will be handled by the

device is Read Status Register.

Write Enable (WEN), Bit 1: This bit represents the

status of device write protection. If WEN = 0, the Status

Register and the entire array is protected from modifica-

tion, regardless of the setting of WPEN, WP pin, or block

protection. The only way to set WEN to 1 is via the

Write Enable command (WREN). WEN is reset to 0

upon power-up.

Block Protect (BP1, BP0), Bits 2-3: Together, these

bits represent one of four block protection configurations

implemented for the memory array. (See Table 2 for

details.)

BP0 and BP1 are non-volatile cells similar to regular

array cells, and factory programmed to 0. The block of

memory defined by these bits is always protected,

regardless of the setting of WPEN, WP , or WEN.

Table 2. Block Protection

Status

Register

Bits

Array Addresses Protected

Level

0

1(1/4)

2(1/2)

3(All)

BP1 BP0

00

01

10

11

IS25C08

None

0300h

-03FFh

0200h

-03FFh

0000h

-03FFh

IS25C16

None

0600h

-07FFh

0400h

-07FFh

0000h

-07FFh

Don’t Care, Bits 4-6: Each of these bits can receive

either 0 or 1, but values will not be retained. When

these bits are read from the register, they are always 0.

Write Protect Enable (WPEN), Bit 7: This bit can be

used in conjunction with WP pin to enable Hardware

Write Protection, which causes the Status Register to

be read-only. The memory array is not protected by this

mode. Hardware Write Protection requires that WP = 0

and WPEN = 1; it is disabled otherwise. Note: WPEN

cannot be changed from 1 to 0 if the WP pin is already

set to Low. (See Table 4 for data protection relationship)

4

Integrated Silicon Solution, Inc. — 1-800-379-4774

Preliminary Information Rev. 00H

02/23/06

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