IS25C64A 查看數據表（PDF） - Integrated Silicon Solution

零件编号

产品描述 (功能)

生产厂家

IS25C64A

32K-BIT/64K-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM

Integrated Silicon Solution 

IS25C32A

IS25C64A

SERIAL INTERFACE DESCRIPTION

MASTER: The device that provides a clock signal.

SLAVE: The IS25C32A/64A is a slave because the

clock signal is an input.

TRANSMITTER/RECEIVER: The IS25C32A/64A has

both data input (SI) and data output (SO).

MSB: The most significant bit. It is always the first bit

transmitted or received.

OP-CODE: The first byte transmitted to the slave

following CS transition to LOW. If the OP-CODE is a

valid member of the IS25C32A/64A instruction set (Table

3), then it is decoded appropriately. If the OP-CODE is

not valid, and the SO pin remains in high impedance.

BLOCK DIAGRAM

STATUS

REGISTER

VCC

GND

8192 x 8/4096 x 8

MEMORY ARRAY

DATA

REGISTER

SI

ADDRESS

DECODER

OUTPUT

BUFFER

MODE

CS

DECODE

LOGIC

WP

SCK

CLOCK

SO

HOLD

Integrated Silicon Solution, Inc.

3

Rev. A

08/14/07

Share Link: