IS25LQ080 查看數據表（PDF） - Integrated Silicon Solution

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IS25LQ080

8 Mbit Single Operating Voltage Serial Flash Memory With 104 MHz Dual- or 100MHz Quad-Output SPI Bus Interface

Integrated Silicon Solution 

IS25LQ080

SPI MODES DESCRIPTION

Multiple IS25LQ080 devices can be connected on the

SPI serial bus and controlled by a SPI Master, i.e.

microcontroller, as shown in Figure 1. The devices

support either of two SPI modes:

Mode 0 (0, 0)

Mode 3 (1, 1)

The difference between these two modes is the clock

polarity when the SPI master is in Stand-by mode: the

serial clock remains at “0” (SCK = 0) for Mode 0 and

the clock remains at “1” (SCK = 1) for Mode 3. Please

refer to Figure 2. For both modes, the input data is

latched on the rising edge of Serial Clock (SCK), and

the output data is available from the falling edge of

SCK.

Figure 1. Connection Diagram among SPI Master and SPI Slaves (Memory Devices)

SPI Interface with

(0,0) or (1,1)

SDI

SDI

SCK

SPI Master

(i.e. Microcontroller)

CS3 CS2 CS1

SCK SO SI

SCK SO SI

SCK SO SI

SPI Memory

Device

CE# WP#

HOLD#

SPI Memory

Device

CE# WP#

HOLD#

SPI Memory

Device

CE# WP#

HOLD#

Note: 1. The Write Protect (WP#) and Hold (HOLD#) signals should be driven high or low as

appropriate.

Figure 2. SPI Modes Supported

SCK

Mode 0 (0,0)

SCK

Mode 3 (1,1)

SI

Input mode

SO

MSb

MSb

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

10/18/2012

5

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