IS41LV16256B 查看數據表（PDF） - Integrated Silicon Solution
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IS41LV16256B Datasheet PDF : 22 Pages
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IS41LV16256B
ISSI®
256K x 16 (4-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
APRIL 2005
FEATURES
• TTL compatible inputs and outputs
• Refresh Interval: 512 cycles/8 ms
• Refresh Mode : RAS-Only, CAS-before-RAS (CBR),
and Hidden
• JEDEC standard pinout
• Single power supply: 3.3V ± 10%
• Byte Write and Byte Read operation via two CAS
• Lead-free available
DESCRIPTION
The ISSI IS41LV16256B is 262,144 x 16-bit high-perfor-
mance CMOS Dynamic Random Access Memory. Both prod-
ucts offer accelerated cycle access EDO Page Mode. EDO
Page Mode allows 512 random accesses within a single row
with access cycle time as short as 10ns per 16-bit word. The
Byte Write control, of upper and lower byte, makes the
IS41LV16256B ideal for use in 16 and 32-bit wide data bus
systems.
These features make the IS41LV16256B ideally suited for
high band-width graphics, digital signal processing, high-
performance computing systems, and peripheral applications.
KEY TIMING PARAMETERS
The IS41LV16256B is packaged in 40-pin 400-mil SOJ and
TSOP (Type II).
Parameter
-35
-60
Unit
Max. RAS Access Time (tRAC)
Max. CAS Access Time (tCAC)
35
60
ns
11
15
ns
Max. Column Address Access Time (tAA)
18
30
ns
Min. EDO Page Mode Cycle Time (tPC)
14
25
ns
Min. Read/Write Cycle Time (tRC)
60
110
ns
PIN CONFIGURATIONS
40-Pin TSOP (Type II)
40-Pin SOJ
VDD 1
I/O0 2
I/O1 3
I/O2 4
I/O3 5
VDD 6
I/O4 7
I/O5 8
I/O6 9
I/O7 10
NC 11
NC 12
WE 13
RAS 14
NC 15
A0 16
A1 17
A2 18
A3 19
VDD 20
40 GND
39 I/O15
38 I/O14
37 I/O13
36 I/O12
35 GND
34 I/O11
33 I/O10
32 I/O9
31 I/O8
30 NC
29 LCAS
28 UCAS
27 OE
26 A8
25 A7
24 A6
23 A5
22 A4
21 GND
VDD 1
I/O0 2
I/O1 3
I/O2 4
I/O3 5
VDD 6
I/O4 7
I/O5 8
I/O6 9
I/O7 10
NC 11
NC 12
WE 13
RAS 14
NC 15
A0 16
A1 17
A2 18
A3 19
VDD 20
40 GND
39 I/O15
38 I/O14
37 I/O13
36 I/O12
35 GND
34 I/O11
33 I/O10
32 I/O9
31 I/O8
30 NC
29 LCAS
28 UCAS
27 OE
26 A8
25 A7
24 A6
23 A5
22 A4
21 GND
PIN DESCRIPTIONS
A0-A8
I/O0-15
WE
OE
RAS
UCAS
LCAS
VDD
GND
NC
Address Inputs
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Upper Column Address Strobe
Lower Column Address Strobe
Power
Ground
No Connection
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
Rev. B
04/28/05
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