IS42S32200E 查看數據表（PDF） - Integrated Silicon Solution

零件编号

产品描述 (功能)

生产厂家

IS42S32200E

512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM

Integrated Silicon Solution 

IS42S32200E, IS45S32200E

PIN FUNCTIONS

Symbol Pin No. (TSOP)

A0-A10

25 to 27

60 to 66

24

Type

Input Pin

BA0, BA1

CAS

CKE

22,23

18

67

Input Pin

Input Pin

Input Pin

CLK

68

Input Pin

CS

20

Input Pin

DQ0 to

DQ31

DQM0

DQM3

2, 4, 5, 7, 8, 10,11,13

74,76,77,79,80,82,83,85

45,47,48,50,51,53,54,56

31,33,34,36,37,39,40,42

16,28,59,71

DQ Pin

Input Pin

RAS

19

Input Pin

WE

17

Input Pin

Vddq

Vdd

GNDq

GND

3,9,35,41,49,55,75,81

1,15,29,43

6,12,32,38,46,52,78,84

44,58,72,86

Supply Pin

Supply Pin

Supply Pin

Supply Pin

Function (In Detail)

Address Inputs: A0-A10 are sampled during the ACTIVE

command (row-address A0-A10) and READ/WRITE command (A0-A7

with A10 defining auto precharge) to select one location out of the memory array

in the respective bank. A10 is sampled during a PRECHARGE command to deter-

mine if all banks are to be precharged (A10 HIGH) or bank selected by

BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD

MODE REGISTER command.

Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE

or PRECHARGE command is being applied.

CAS, in conjunction with the RAS and WE, forms the device command. See the

"Command Truth Table" for details on device commands.

The CKE input determines whether the CLK input is enabled. The next rising edge

of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE

is LOW, the device will be in either power-down mode, clock suspend mode, or self

refresh mode. CKE is an asynchronous input.

CLK is the master clock input for this device. Except for CKE, all inputs to this device

are acquired in synchronization with the rising edge of this pin.

The CS input determines whether command input is enabled within the device.

Command input is enabled when CS is LOW, and disabled with CS is HIGH. The

device remains in the previous state when CS is HIGH.

DQ0 to DQ15 are DQ pins. DQ through these pins can be controlled in byte units

using the DQM0-DQM3 pins

DQMx control thel ower and upper bytes of the DQ buffers. In read mode,

the output buffers are place in a High-Z state. During a WRITE cycle the input data

is masked. When DQMx is sampled HIGH and is an input mask signal for write

accesses and an output enable signal for read accesses. DQ0 through DQ7 are

controlled by DQM0. DQ8 throughDQ15 are controlled by DQM1. DQ16 through

DQ23 are controlled by DQM2. DQ24 through DQ31 are controlled by DQM3.

RAS, in conjunction with CAS and WE, forms the device command. See the "Com-

mand Truth Table" item for details on device commands.

WE, in conjunction with RAS and CAS, forms the device command. See the "Com-

mand Truth Table" item for details on device commands.

Vddq is the output buffer power supply.

Vdd is the device internal power supply.

GNDq is the output buffer ground.

GND is the device internal ground.

Integrated Silicon Solution, Inc. — www.issi.com

5

Rev.  B

07/23/09

Share Link: