IS61C256AL 查看數據表（PDF） - Integrated Silicon Solution

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IS61C256AL

32K x 8 HIGH-SPEED CMOS STATIC RAM

Integrated Silicon Solution 

IS61C256AL

ISSI ®

WRITE CYCLE NO. 2 (OE is HIGH During Write Cycle) (1,2)

ADDRESS

OE

t WC

VALID ADDRESS

t HA

CE LOW

WE

DOUT

t SA

DATA UNDEFINED

t AW

t PWE1

t HZWE

DIN

HIGH-Z

t LZWE

t SD

t HD

DATAIN VALID

CE_WR2.eps

WRITE CYCLE NO. 3 (OE is LOW During Write Cycle) (1)

ADDRESS

OE LOW

t WC

VALID ADDRESS

t HA

CE LOW

WE

DOUT

t SA

DATA UNDEFINED

DIN

t AW

t PWE2

t HZWE

HIGH-Z

t LZWE

t SD

t HD

DATAIN VALID

CE_WR3.eps

Notes:

1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,

but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling

edge of the signal that terminates the Write.

2. I/O will assume the High-Z state if OE ≥ VIH.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

7

Rev. B

10/23/06

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