EVAL-AD7856CB 查看數據表（PDF） - Analog Devices

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EVAL-AD7856CB

5 V Single Supply, 8-Channel 14-Bit 285 kSPS Sampling ADC

Analog Devices 

AD7856

Parameter

A Version1

K Version1 Units

Test Conditions/Comments

POWER PERFORMANCE

AVDD, DVDD

IDD

Normal Mode5

Sleep Mode6

With External Clock On

With External Clock Off

Normal Mode Power Dissipation

Sleep Mode Power Dissipation

With External Clock On

With External Clock Off

+4.75/+5.25

17

30

400

5

200

89.25

52.5

26.25

+4.75/+5.25 V min/max

17

10

500

5

200

89.25

52.5

26.25

mA max

µA typ

µA typ

µA max

µA typ

mW max

µW typ

µW max

AVDD = DVDD = 4.75 V to 5.25 V. Typically 12 mA

Full Power-Down. Power Management Bits in Con-

trol Register Set as PMGT1 = 1, PMGT0 = 0

Partial Power-Down. Power Management Bits in

Control Register Set as PMGT1 = 1, PMGT0 = 1

Typically 0.5 µA. Full Power-Down. Power Manage-

ment. Bits in Control Register Set as PMGT1 = 1,

PMGT0 = 0

Partial Power-Down. Power Management Bits in

Control Register Set as PMGT1 = 1, PMGT0 = 1

VDD = 5.25 V. Typically 60 mW; SLEEP = VDD

VDD = 5.25 V. SLEEP = 0 V

VDD = 5.25 V. Typically 5.25 µW; SLEEP = 0 V

SYSTEM CALIBRATION

Offset Calibration Span7

Gain Calibration Span7

+0.0375 × VREF/–0.0375 × VREF V max/min Allowable Offset Voltage Span for Calibration

+1.01875 × VREF/–0.98125 × VREF V max/min Allowable Full-Scale Voltage Span for Calibration

NOTES

1Temperature ranges as follows: A Version: –40°C to +105°C. K Version: 0°C to +105°C.

2Specifications apply after calibration.

3SNR calculation includes distortion and noise components.

4Sample tested @ +25°C to ensure compliance.

5All digital inputs @ DGND except for CONVST, SLEEP, CAL and SYNC @ DVDD. No load on the digital outputs. Analog inputs @ AGND.

6CLKIN @ DGND when external clock off. All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DVDD. No load on the digital outputs.

Analog inputs @ AGND.

7The Offset and Gain Calibration Spans are defined as the range of offset and gain errors that the AD7856 can calibrate. Note also that these are voltage spans and are

not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–) ± 0.0375 × VREF, and

the allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be V REF ± 0.01875 × VREF).

This is explained in more detail in the Calibration section of the data sheet.

Specifications subject to change without notice.

REV. A

–3–

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