EVAL-AD7856CB 查看數據表（PDF） - Analog Devices
零件编号
产品描述 (功能)
生产厂家
EVAL-AD7856CB Datasheet PDF : 32 Pages
| |||
AD7856
ON-CHIP REGISTERS
The AD7856 powers up with a set of default conditions. The only writing that is required is to select the channel configuration.
Without performing any other write operations the AD7856 still retains the flexibility for performing a full power-down, and a full
self-calibration.
Extra features and flexibility such as performing different power-down options, different types of calibrations including system cali-
bration, and software conversion start can be selected by further writing to the part.
The AD7856 contains a Control Register, ADC Output Data Register, Status Register, Test Register and ten Calibration
Registers. The control register is write only, the ADC output data register and the status register are read only, and the test and
calibration registers are both read/write registers. The Test Register is used for testing the part and should not be written to.
Addressing the On-Chip Registers
Writing
A write operation to the AD7856 consists of 16 bits. The two MSBs, ADDR0 and ADDR1, are decoded to determine which register
is addressed, and the subsequent 14 bits of data are written to the addressed register. It is not until all 16 bits are written that the
data is latched into the addressed registers. Table I shows the decoding of the address bits while Figure 4 shows the overall write
register hierarchy.
ADDR1
0
0
1
1
ADDR0
0
1
0
1
Table I. Write Register Addressing
Comment
This combination does not address any register so the subsequent 14 data bits are ignored.
This combination addresses the TEST REGISTER. The subsequent 14 data bits are written to the
test register.
This combination addresses the CALIBRATION REGISTERS. The subsequent 14 data bits are
written to the selected calibration register.
This combination addresses the CONTROL REGISTER. The subsequent 14 data bits are written
to the control register.
Reading
To read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. These
bits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read address
bits while Figure 5 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will be
from the ADC output data register.
Once the read selection bits are set in the Control Register, all subsequent read operations that follow will be from the selected regis-
ter until the read selection bits are changed in the Control Register.
RDSLT1
0
0
1
1
RDSLT0
0
1
0
1
Table II. Read Register Addressing
Comment
All successive read operations will be from ADC OUTPUT DATA REGISTER. This is the power-
up default setting. There will always be two leading zeros when reading from the ADC Output Data
Register.
All successive read operations will be from TEST REGISTER.
All successive read operations will be from CALIBRATION REGISTERS.
All successive read operations will be from STATUS REGISTER.
ADDR1, ADDR0
DECODE
RDSLT1, RDSLT0
DECODE
01
TEST
REGISTER
10
CALIBRATION
REGISTERS
11
CONTROL
REGISTER
00
ADC OUTPUT
DATA REGISTER
01
TEST
REGISTER
10
CALIBRATION
REGISTERS
11
STATUS
REGISTER
CALSLT1, CALSLT0
DECODE
GAIN(1)
OFFSET(1)
DAC(8)
00
GAIN(1)
OFFSET(1)
01
OFFSET(1)
10
GAIN(1)
11
Figure 4. Write Register Hierarchy/Address Decoding
CALSLT1, CALSLT0
DECODE
GAIN(1)
OFFSET(1)
DAC(8)
00
GAIN(1)
OFFSET(1)
01
OFFSET(1)
10
GAIN(1)
11
Figure 5. Read Register Hierarchy/Address Decoding
REV. A
–9–
Share Link: 