IS93C46A 查看數據表（PDF） - Integrated Silicon Solution

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IS93C46A

1,024/2,048/4,096-BIT SERIAL ELECTRICALLY ERASABLE PROM

Integrated Silicon Solution 

IS93C46A IS93C56A IS93C66A

ISSI ®

Write Enable (WEN)

The write enable (WEN) instruction must be executed

before any device programming (WRITE, WRALL,

ERASE, and ERAL) can be done. When Vcc is applied,

this device powers up in the write disabled state. The

device then remains in a write disabled state until a WEN

instruction is executed. Thereafter, the device remains

enabled until a WDS instruction is executed or until Vcc

is removed. (See Figure 4.) (Note: Chip select must

remain LOW until Vcc reaches its operational value.)

Write (WRITE)

The WRITE instruction includes 8 or 16 bits of data to be

written into the specified register. After the last data bit

has been applied to DIN, and before the next rising edge

of SK, CS must be brought LOW. The falling edge of CS

initiates the self-timed programming cycle.

If CS is brought HIGH, after a minimum wait of 250 ns

(5V operation) after the falling edge of CS (tCS) DOUT will

indicate the READY/BUSY status of the chip. Logical

“0” means programming is still in progress, logical “1”

means the selected register has been written, and the

part is ready for another instruction (see Figure 5).

(NOTE: The combination of CS HIGH, DIN HIGH and

the rising edge of the SK clock, resets the READY/

BUSY flag. Therefore, to access the READY/BUSY

flag, this combination of control signals should be

avoided.) Before a WRITE instruction can be executed,

the device must be write enabled (see WEN).

Write All (WRALL)

The write all (WRALL) instruction programs all registers

with the data pattern specified in the instruction. As with

the WRITE instruction, the falling edge of CS must occur

to initiate the self-timed programming cycle. If CS is then

brought HIGH after a minimum wait of 250 ns (tCS), the

DOUT pin indicates the READY/BUSY status of the chip (see

Figure 6).

Write Disable (WDS)

The write disable (WDS) instruction disables all programming

capabilities. This protects the entire device against acci-

dental modification of data until a WEN instruction is

executed. (When Vcc is applied, this part powers up in the

write disabled state.) To protect data, a WDS instruction

should be executed upon completion of each programming

operation.

Erase Register (ERASE)

After the erase instruction is entered, CS must be brought

LOW. The falling edge of CS initiates the self-timed internal

programming cycle. Bringing CS HIGH after a minimum of

tCS, will cause DOUT to indicate the READ/BUSY status of the

chip: a logical “0” indicates programming is still in progress;

a logical “1” indicates the erase cycle is complete and the

part is ready for another instruction (see Figure 8).

Erase All (ERAL)

Full chip erase is provided for ease of programming. Erasing

the entire chip involves setting all bits in the entire memory

array to a logical “1” (see Figure 9).

INSTRUCTION SET - IS93C46A

Instruction

Start Bit

READ

1

WEN (Write Enable)

1

WRITE

1

WRALL (Write All Registers) 1

WDS (Write Disable)

1

ERASE

1

ERAL (Erase All Registers) 1

OP Code

10

00

01

00

00

11

00

8-bit Organization

(ORG = GND)

Address (1) Input Data

(A6-A0)

—

11xxxxx

—

(A6-A0)

(D7-D0) (3)

01xxxxx (D7-D0) (3)

00xxxxx

—

(A6-A0)

—

10xxxxx

—

16-bit Organization

(ORG = Vcc)

Address (1) Input Data

(A5-A0)

—

11xxxx

—

(A5-A0) (D15-D0) (2)

01xxxx (D15-D0) (2)

00xxxx

—

(A5-A0)

—

10xxxx

—

Notes:

1. x = Don't care bit.

2. If input data is not 16 bits exactly, the last 16 bits will be taken as input data.

3. If input data is not 8 bits exactly, the last 8 bits will be taken as input data.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

3

Rev. A

11/12/02

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