ISL12028(2006) 查看數據表（PDF） - Intersil

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ISL12028
(Rev.:2006)

Real Time Clock/Calendar with EEPROM

Intersil 

Timing Diagrams

SCL

tSU:STA

SDA

(INPUT TIMING)

SDA

(OUTPUT TIMING)

ISL12028

tF

tHIGH

tSU:DAT

tHD:STA

tLOW

tR

tHD:DAT

tAA

tDH

FIGURE 1. BUS TIMING

tHD:STO

tSU:STO

tBUF

SCL

SDA

8TH BIT OF LAST BYTE

ACK

tWC

STOP

CONDITION

FIGURE 2. WRITE CYCLE TIMING

START

CONDITION

SCL

SDA

tRSP

tRSP<tWDO

tRSP>tWDO

tRST

tRSP>tWDO

tRST

RESET

START

STOP START

Note: All inputs are ignored during the active reset period (tRST).

FIGURE 3. WATCHDOG TIMING

VRESET

VDD

tPURST

tR

RESET

7

tRPD

tPURST

FIGURE 4. RESET TIMING

tF

VRVALID

FN8233.5

October 18, 2006

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