ISL3685 查看數據表（PDF） - Intersil

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ISL3685

2.4GHz RF/IF Converter and Synthesizer

Intersil 

DATA BIT 20: MSB

BIT 19

ISL3685

BIT 10 BIT 9

BIT 1

CLOCK

LE

tCS

tCH

OR

LE

tCWL

tCWH

tES

NOTES:

8. Parenthesis data indicates programmable reference divider data.

9. Data shifted into register on clock rising edge.

10. Data is shifted in MSB first.

FIGURE 1. SERIAL DATA INPUT TIMING

BIT 1: LSB

tEW

fR

fP

LD

DO

H

I

I

I

Z

L

fR > fP

fR = fP

fR < fP

fR < fP

fR < fP

NOTES:

11. Phase difference detection range: -2π to +2π.

12. The minimum width pump up and pump down current pulses occur at the DO pin when the loop is locked.

FIGURE 2. PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS

8

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