ISL8016 查看數據表（PDF） - Intersil
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ISL8016 Datasheet PDF : 22 Pages
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ISL8016
Negative Current Protection
Similar to the overcurrent, the negative current protection is
realized by monitoring the current across the low-side N-FET, as
shown in Figure 4. When the valley point of the inductor current
reaches -3A for 4 consecutive cycles, both P-FET and N-FET are off.
The 100Ω in parallel to the N-FET will activate discharging the
output into regulation. The control will begin to switch when output
is within regulation. The regulator will be in PFM for 20µs before
switching to PWM if necessary.
PG
PG is an open-drain output of a window comparator that
continuously monitors the buck regulator output voltage. PG is
actively held low when EN is low and during the buck regulator
soft-start period. After 1ms delay of the soft-start period, PG
becomes high impedance as long as the output voltage is within
nominal regulation voltage set by VFB. When VFB drops 15%
below or raises 0.8V above the nominal regulation voltage, the
ISL8016 pulls PG low. Any fault condition forces PG low until the
fault condition is cleared by attempts to soft-start. For logic level
output voltages, connect an external pull-up resistor, R1, between
PG and VIN. A 100kΩ resistor works well in most applications.
UVLO
When the input voltage is below the undervoltage lock-out (UVLO)
threshold, the regulator is disabled.
Soft Start-Up
The soft start-up reduces the in-rush current during the start-up.
The soft-start block outputs a ramp reference to the input of the
error amplifier. This voltage ramp limits the inductor current as
well as the output voltage speed so that the output voltage rises
in a controlled fashion. When VFB is less than 0.1V at the
beginning of the soft-start, the switching frequency is reduced to
200kHz so that the output can start-up smoothly at light load
condition. During soft-start, the IC operates in the SKIP mode to
support pre-biased output condition.
Tie SS to SGND for an internal soft-start of approximately 1ms.
Connect a capacitor from SS to SGND to adjust the soft-start
time. This capacitor, along with an internal 1.6µA current source
sets the soft-start interval of the converter, tSS.
CSS[μF] = 3.33 ⋅ tSS[s]
(EQ. 3)
CSS must be less than 33nF to insure proper soft-start reset after
fault condition.
Figure 38 is a comparison between measured and calculated
output soft-start time versus Css capacitance.
18
15
12
9
SS (ms)
MEASUREMENT
6
SS (ms)
3
CALCULATION
0
0
8
16
24
32
40
48
CSS (nF)
FIGURE 38. SOFT-START TIME vs CSS
Enable
The enable (EN) input allows the user to control the turning on or
off of the regulator for purposes such as power-up sequencing.
When the regulator is enabled, there is typically a 600µs delay
for waking up the bandgap reference and then the soft start-up
begins.
Discharge Mode (Soft-Stop)
When a transition to shutdown mode occurs or the VIN UVLO is
set, the outputs discharge to GND through an internal 100Ω
switch. The discharge mode is disabled if SS is tied to an external
capacitor.
Power MOSFETs
The power MOSFETs are optimized for best efficiency. The
ON-resistance for the P-FET is typically 30mΩ and the
ON-resistance for the N-FET is typically 20mΩ.
100% Duty Cycle
The ISL8016 features 100% duty cycle operation to maximize
the battery life. When the battery voltage drops to a level that the
ISL8016 can no longer maintain the regulation at the output, the
regulator completely turns on the P-FET. The maximum dropout
voltage under the 100% duty-cycle operation is the product of the
load current and the ON-resistance of the P-FET.
Thermal Shutdown
The ISL8016 has built-in thermal protection. When the internal
temperature reaches +150°C, the regulator is completely shut
down. As the temperature drops to +125°C, the ISL8016 resumes
operation by stepping through the soft-start.
17
FN7616.1
May 5, 2011
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