ISL8016 查看數據表（PDF） - Intersil
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ISL8016 Datasheet PDF : 22 Pages
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ISL8016
PWM COMPARATOR GAIN Fm:
The PWM comparator gain Fm for peak current mode control is
given by Equation 6:
Fm = v-ˆ--c---o-d-ˆ-m-----p-- = -(--S----e----+---1--S---n----)--T---s-
(EQ. 6)
Where, Se is the slew rate of the slope compensation and Sn is
given by Equation 7:
Sn
=
Rt
V----i--n----–-----V---o-
LP
(EQ. 7)
Where Rt is trans-resistance, which is the gain of the current
amplifier.
CURRENT SAMPLING TRANSFER FUNCTION He(S):
In current loop, the current signal is sampled every switching
cycle. It has the following transfer function:
He(S)=
-S----2-
ωn2
+
------S-------
ωnQn
+
1
(EQ. 8)
where Qn and ωn are given by Qn = –2-π- , ωn= πfs
Power Stage Transfer Functions
Transfer function F1(S) from control to output voltage is:
F1(S)
=
v-ˆ-d-ˆ-o-
=
Vi
n
---------1-----+------ω--------Se------s------r---------
-S----2-
ωo2
+
-ω----o-S--Q----p-
+
1
(EQ. 9)
Where
ωesr
=
------1------
RcCo
,Qp
≈
Ro
C----o-
LP
,ωo=
--------1--------
LPCo
Transfer function F2(S) from control to inductor current is given
by Equation 10:
F2(S)
= ˆI-d-ˆo--
=
--------V----i-n---------
Ro + RLP
------------1-----+-----ω---S------z------------
-S----2-
ωo2
+
-ω----o-S--Q----p-
+
1
(EQ. 10)
where
ωz
=
------1-------
RoCo
.
Current loop gain Ti(S) is expressed as Equation 11:
Ti(S) = RtFmF2(S)He(S)
(EQ. 11)
The voltage loop gain with open current loop is:
Tv(S) = KFmF1(S)Av(S)
(EQ. 12)
The Voltage loop gain with current loop closed is given by
Equation 13:
Lv(S)
=
-----T---v---(--S----)-----
1 + Ti(S)
(EQ. 13)
Where
K
=
-V---F---B-- ,
Vo
VFB
is the feedback voltage of the voltage
error amplifier. If Ti(S)>>1, then Equation 13 can be simplified by
Equation 14:
Lv(S)=
-V---F---B--
Vo
-R----o----+-----R----L---P-
Rt
1------+------ω--------Se------s------r
1
+
--S----
ωp
-A----v--(---S----)
He(S)
,
ωp
≈
------1-------
RoCo
(EQ. 14)
From Equation 14, it is shown that the system is a single order
system, which has a single pole located at ωp before the half
switching frequency. Therefore, a simple type II compensator can
be easily used to stabilize the system.
Vo
R2
C3
VFB -
VCOMP
R3
VREF
GM
+
R6
C7
C6
FIGURE 41. TYPE II COMPENSATOR
Figure 41 shows the type II compensator and its transfer function
is expressed as follows:
Av(S)=
-vˆ--c-v-ˆ-o-F--m-B----p-- =
------G----M---------
C6 + C7
⎝⎛---1-----+-----ω----------cS-----z-----1-----⎠⎞---⎝⎛---1-----+-----ω----------cS------z----2-----⎠⎞-
S
⎛
⎝
1
+
ω----S-c---p-⎠⎞
Where
ωcz1
=
------1------- ,
R6C6
ωcz2 =
------1------- ,
R2C3
ωcp
=
-C----6-----+-----C---7---
R6C6C7
Compensator design goal:
(EQ. 15)
High DC gain
Loop bandwidth fc:
⎛
⎝
1--
4
t
o
1--1--0--⎠⎞
fs
Gain margin: >10dB
Phase margin: 40°
The compensator design procedure is as follows:
Put compensator zero
ωcz1=
(1to3) ------1-------
RoCo
Put one compensator pole at zero frequency to achieve high DC
gain, and put another compensator pole at either ESR zero
frequency or half switching frequency, whichever is lower. An
optional zero can boost the phase margin. ωCZ2 is a zero due to
R2 and C3.
Put compensator zero
ωcz2=
(5to8) ------1-------
RoCo
The loop gain Tv(S) at cross over frequency of fc has unity gain.
Therefore, the compensator resistance R6 is determined by:
R6
=
-2---π----f--c---V----o---C----o---R----t
GM ⋅ VFB
(EQ. 16)
19
FN7616.1
May 5, 2011
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