SCN2651 查看數據表（PDF） - Philips Electronics
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SCN2651 Datasheet PDF : 15 Pages
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Philips Semiconductors
Programmable communications interface (PCI)
Product specification
SCN2651
PIN DESCRIPTION
Pin No.
27, 28, 1, 2, 5-8
21
12, 10
13
11
22
24
23
17
16
18
9
25
19
3
15
14
20
26
4
Symbol
D0 – D7
RESET
A0–A1
R/W
CE
DSR
DTR
RTS
CTS
DCD
TxEMT/DSCHG
TxC
RxC
TxD
RxD
TxRDY
RxRDY
BRCLK
VCC
GND
Name and Function
8-Bit data bus
Reset
Internal register select lines
Read or write command
Chip enable input
Data set ready
Data terminal ready
Request to send
Clear to send
Data carrier detected
Transmitter empty or data set change
Transmitter clock
Receiver clock
Transmitter data
Receiver data
Transmitter ready
Receiver ready
Baud rate generator clock
+5V supply
Ground
Type
I/O
I
I
I
I
I
O
O
I
I
O
I/O
I/O
O
I
O
O
I
I
I
Table 1. Baud Rate Generator Characteristics
Crystal Frequency = 5.0688MHz
Baud
Rate
Theoretical
Frequency
16X Clock
Actual
Frequency
16X Clock
Percent
Error
Divisor
50
0.8kHz
0.8kHz
–
6336
75
1.2
1.2
–
4224
110
1.76
1.76
–
2880
134.5
2.152
2.1523
0.016
2355
150
2.4
2.4
–
2112
300
4.8
4.8
–
1056
600
9.6
9.6
–
528
1200
19.2
19.2
–
264
1800
28.8
28.8
–
176
2000
32.0
32.081
0.253
158
2400
38.4
38.4
–
132
NOTE: *Error at 19200 can be reduced to zero by using crystal
frequency 4.9152MHz. 16X clock is used in asynchronous mode.
In synchronous mode, clock multiplier is 1X.
BLOCK DIAGRAM
The PCI consists of six major sections. These are the transmitter,
receiver, timing, operation control, modem control and SYN/DLE
control. These sections communicate with each other via an
internal data bus and an internal control bus. The internal data bus
interfaces to the microprocessor data bus via a data bus buffer.
Operation Control
This functional block stores configuration and operation commands
from the CPU and generates appropriate signals to various internal
sections to control the overall device operation. It contains read and
write circuits to permit communications with the microprocessor via
the data bus and contains mode registers 1 and 2, the command
register, and the status register. Details of register addressing and
protocol are presented in the PCI programming section of this data
sheet.
Timing
The PCI contains a baud rate generator (BRG) which is
programmable to accept external transmit or receive clocks or to
divide an external clock to perform data communications. The unit
can generate 16 commonly used baud rates, any one of which can
be selected for full-duplex operation. See Table 1.
Receiver
The receiver accepts serial data on the RxD pin, converts this serial
input to parallel format, checks for bits or characters that are unique
to the communication technique and sends an “assembled”
character to the CPU.
Transmitter
The transmitter accepts parallel data from the CPU, converts it to a
serial bit stream, inserts the appropriate characters or bits (based on
the communication technique) and outputs a composite serial
stream of data on the TxD output pin.
Modem Control
The modem control section provides interfacing for three input
signals and three output signals used for “handshaking” and status
indication between the CPU and a modem.
SYN/DLE Control
This section contains control circuitry and three 8-bit registers
storing the SYN1, SYN2, and DLE characters provided by the CPU.
These registers are used in the synchronous mode of operation to
provide the characters required for synchronization, idle fill and data
transparency.
1994 Apr 27
4
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