ISPGDX160V-9Q208I 查看數據表（PDF） - Lattice Semiconductor

零件编号

产品描述 (功能)

生产厂家

ISPGDX160V-9Q208I

In-System Programmable 3.3V Generic Digital Crosspoint

Lattice Semiconductor 

Specifications ispGDX160V/VA

Architecture

The ispGDXV/VA architecture is different from traditional The various I/O pin sets are also shown in the block

PLD architectures, in keeping with its unique application diagram below. The A, B, C, and D I/O pins are grouped

focus. The block diagram is shown below. The program- together with one group per side.

mable interconnect consists of a single Global Routing

Pool (GRP). Unlike ispLSI® devices, there are no pro-

grammable logic arrays on the device. Control signals for

OEs, Clocks/Clock Enables and MUX Controls must

S come from designated sets of I/O pins. The polarity of

these signals can be independently programmed in each

I/O cell.

E Each I/O cell drives a unique pin. The OE control for each

I/O pin is independent and may be driven via the GRP by

IC one of the designated I/O pins (I/O-OE set). The I/O-OE

set consists of 25% of the total I/O pins. Boundary Scan

D test is supported by dedicated registers at each I/O pin.

In-system programming is accomplished through the

V E standard Boundary Scan protocol.

I/O Architecture

Each I/O cell contains a 4:1 dynamic MUX controlled by

two select lines as well as a 4x4 crossbar switch con-

trolled by software for increased routing flexiability (Figure

1). The four data inputs to the MUX (called M0, M1, M2,

and M3) come from I/O signals in the GRP and/or

adjacent I/O cells. Each MUX data input can access one

quarter of the total I/Os. For example, in a 160 I/O

ispGDXV, each data input can connect to one of 40 I/O

pins. MUX0 and MUX1 can be driven by designated I/O

pins called MUXsel1 and MUXsel2. Each MUXsel input

covers 25% of the total I/O pins (e.g. 40 out of 160). MUX0

and MUX1 can be driven from either MUXsel1 or MUXsel2.

Figure 1. ispGDXV/VA I/O Cell and GRP Detail (160 I/O Device)

E U Logic“0” Logic“1”

160 I/O Inputs

D IN I/OCell0

I/O Cell 159

I/O Cell 1

ECT ONT ••

L •••

E C •

E2CMOS

Programmable

Interconnect

I/O Group A

I/O Group B

I/O Group C

I/O Group D

I/O Cell 158

•••

From MUX Outputs

of 2 Adjacent I/O Cells

N+2

N+1

4x4

Crossbar

Switch

N-1

N-2

To 2 Adjacent

I/O Cells above

Bypass Option

4-to-1 MUX

M0

M1

M2

M3

MUX0 MUX1

Register

or Latch

A

C

BD

QR

CLK

Prog. Prog.

Pull-up Bus Hold

(VCCIO) Latch

I/O

Pin

Prog. Open Drain

From MUX Outputs

of 2 Adjacent I/O Cells

To 2 Adjacent

I/O Cells below

CLK_EN Reset

2.5V/3.3V Output

Prog. Slew Rate

Boundary

Scan Cell

S IS I/OCellN

D •••

I/O Cell 78

I/O Cell 79

80 I/O Cells

••••••

160 Input GRP

Inputs Vertical

Outputs Horizontal

Global

Y0-Y3 Reset

Global

Clocks /

Clock_Enables

I/O Cell 81

80 I/O Cells

I/O Cell 80

ispGDXV/VA architecture enhancements over ispGDX (5V)

3

Share Link: