ISPGDX160V-9Q208I 查看數據表（PDF） - Lattice Semiconductor
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ISPGDX160V-9Q208I Datasheet PDF : 36 Pages
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Specifications ispGDX160V/VA
Applications (Continued)
Figure 5. Address Demultiplex/Data Buffering
Designing with the ispGDXV/VA
As mentioned earlier, this architecture satisfies the PRSI
XCVR
I/OA I/OB
OEA OEB
ES Address
Latch
D
Q
IC CLK
Buffered
Data
To Memory/
Peripherals
Address
V ED Figure 6. Data Bus Byte Swapper
E U D0-7
XCVR
I/OA I/OB
OEA OEB
CT DNTIN D8-15
XCVR
I/OA I/OB
OEA OEB
D0-7
XCVR
I/OA I/OB
OEA OEB
D8-15
XCVR
I/OA I/OB
OEA OEB
LE O Figure 7. Four-Port Memory Interface
E C 4-to-1
16-Bit MUX
Bidirectional
S ISPort#1
OE1
Memory
Port
Port #2
DOE2
OEM
To
Memory
class of applications without restrictions: any I/O pin as a
single input or bidirectional can drive any other I/O pin as
output.
For the case of PDP applications, the designer does have
to take into consideration the limitations on pins that can
be used as control (MUX0, MUX1, OE, CLK) or data
(MUXA-D) inputs. The restrictions on control inputs are
not likely to cause any major design issues because the
input possibilities span 25% of the total pins.
The MUXA-D input partitioning requires that designers
consciously assign pinouts so that MUX inputs are in the
appropriate, disjoint groups. For example, since the
MUXA group includes I/O0-39 (160 I/O device), it is not
possible to use I/O0 and I/O9 in the same MUX function.
As previously discussed, data path functions will be
assigned early in the design process and these restric-
tions are reasonable in order to optimize speed and cost.
User Electronic Signature
The ispGDXV/VA Family includes dedicated User Elec-
tronic Signature (UES) E2CMOS storage to allow users
to code design-specific information into the devices to
identify particular manufacturing dates, code revisions,
or the like. The UES information is accessible through
the boundary scan programming port via a specific com-
mand. This information can be read even when the
security cell is programmed.
Security
The ispGDXV/VA Family includes a security feature that
prevents reading the device program once set. Even
when set, it does not inhibit reading the UES or device ID
code. It can be erased only via a device bulk erase.
Port #3
SEL0
OE3
Port #4
OE4
SEL1
Note: All OE and SEL lines driven by external arbiter logic (not shown).
7
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