LX64EV-5F100I 查看數據表（PDF） - Lattice Semiconductor

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LX64EV-5F100I

High Performance Interfacing and Switching

Lattice Semiconductor 

Lattice Semiconductor

Figure 1. ispGDX2 Block Diagram (256-I/O Device)

ispGDX2 Family Data Sheet

sysIO Bank

sysIO Bank

sysCLOCK

PLL

sysHSI

Block

SERDES

FIFO

SERDES

FIFO

SERDES

FIFO

SERDES

sysHSI

Block

FIFO

sysCLOCK

PLL

GDX Block GDX Block GDX Block GDX Block

Global Routing Pool

(GRP)

GDX Block GDX Block GDX Block GDX Block

sysCLOCK

PLL

FIFO

sysHSI

Block

SERDES

FIFO

SERDES

sysIO Bank

FIFO

SERDES

FIFO

SERDES

sysHSI

Block

sysCLOCK

PLL

sysIO Bank

ISP & Boundary Scan

Test Port

Introduction

The ispGDX2™ family is Lattice’s second generation in-system programmable generic digital crosspoint switch for

high speed bus switching and interface applications.

The ispGDX2 family is available in two options. The standard device supports sysHSI capability for ultra fast serial

communications while the lower-cost “E-series” supports the same high-performance FPGA fabric without the

sysHSI Block.

This family of switches combines a flexible switching architecture with advanced sysIO interfaces including high

performance sysHSI Blocks, and sysCLOCK PLLs to meet the needs of the today’s high-speed systems. Through

a muliplexer-intensive architecture, the ispGDX2 facilitates a variety of common switching functions.

The availability of on-chip control logic further enhances the power of these devices. A high-performance solution,

the family supports bandwidth up to 38Gbps.

Every device in the family has a number of PLLs to provide the system designer with the ability to generate multiple

clocks and manage clock skews in their systems.

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